86da20b| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 34.000s | 2.654ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 23.997us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 12.243us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 64.276us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 13.759us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 3.111us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 12.243us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 13.759us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 54.000s | 5.516ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 11.000s | 170.790us | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 10.000s | 230.954us | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 50.762us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 4.000s | 1.674us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 4.000s | 1.674us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 23.997us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 12.243us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 13.759us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 26.908us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 23.997us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 12.243us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 13.759us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 26.908us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 4.000s | 99.998us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 7.156us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_intg_err has 1 failures.
0.mbx_tl_intg_err.70020829461387482195573938009404750851281552921927655123455380061947927368821
Line 99, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 7156239 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x1048ad10 a_data = 0x5bb277a6 a_mask = 0xe a_size = 0x2 a_param = 0x0 a_source = 0x27 a_opcode = PutPartialData a_user = 0x2768a d_data = 0xeb7c2e37 d_size = 0x2 d_param = 0x0 d_source = 0x6f d_opcode = AccessAck d_error = 0 d_user = 110000110110 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 7156239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_csr_mem_rw_with_rand_reset has 1 failures.
0.mbx_csr_mem_rw_with_rand_reset.54907602120215706448750543817265576574493646024940293814165134296627248563062
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 3111495 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xf3025b48 a_data = 0xca5b4c64 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x6d a_opcode = PutPartialData a_user = 0x1f16a d_data = 0x8d66b518 d_size = 0x1 d_param = 0x0 d_source = 0x81 d_opcode = AccessAck d_error = 0 d_user = 1001010110001 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 3111495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutFullData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.61507836516363811075446599987321534133004326761061048131209174212557653715152
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 1673895 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xdba67490 a_data = 0x8dc305af a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x24 a_opcode = PutFullData a_user = 0x1b38d d_data = 0xb428678b d_size = 0x0 d_param = 0x0 d_source = 0xa8 d_opcode = AccessAck d_error = 0 d_user = 1011000100011 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1673895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---