ROM_CTRL/32KB Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.810s 135.695us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.260s 147.845us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.740s 180.829us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 5.750s 539.880us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.810s 263.626us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.860s 156.010us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.740s 180.829us 1 1 100.00
rom_ctrl_csr_aliasing 4.810s 263.626us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.550s 557.645us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.480s 560.373us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 5.200s 137.657us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 12.960s 679.738us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 9.570s 222.610us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.660s 299.659us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 5.790s 533.352us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 5.790s 533.352us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.260s 147.845us 1 1 100.00
rom_ctrl_csr_rw 4.740s 180.829us 1 1 100.00
rom_ctrl_csr_aliasing 4.810s 263.626us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.980s 988.938us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.260s 147.845us 1 1 100.00
rom_ctrl_csr_rw 4.740s 180.829us 1 1 100.00
rom_ctrl_csr_aliasing 4.810s 263.626us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.980s 988.938us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.512m 5.849ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 14.890s 691.480us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.547m 313.734us 1 1 100.00
rom_ctrl_tl_intg_err 44.450s 557.063us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.547m 313.734us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.547m 313.734us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.512m 5.849ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.512m 5.849ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.512m 5.849ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.512m 5.849ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.512m 5.849ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.547m 313.734us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.547m 313.734us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.810s 135.695us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.810s 135.695us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.810s 135.695us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 44.450s 557.063us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.512m 5.849ms 1 1 100.00
rom_ctrl_kmac_err_chk 9.570s 222.610us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.512m 5.849ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.512m 5.849ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.512m 5.849ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 14.890s 691.480us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.547m 313.734us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.206m 11.822ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00