ROM_CTRL/64KB Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.800s 298.463us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.350s 1.122ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.330s 239.068us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.040s 1.112ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.820s 215.177us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.630s 379.043us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.330s 239.068us 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 215.177us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.800s 217.730us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.140s 315.063us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.470s 224.749us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 19.020s 601.275us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 16.490s 581.918us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.720s 299.399us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.750s 376.823us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.750s 376.823us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.350s 1.122ms 1 1 100.00
rom_ctrl_csr_rw 6.330s 239.068us 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 215.177us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.860s 1.539ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.350s 1.122ms 1 1 100.00
rom_ctrl_csr_rw 6.330s 239.068us 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 215.177us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.860s 1.539ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.055m 12.370ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 21.720s 5.312ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.646m 4.172ms 1 1 100.00
rom_ctrl_tl_intg_err 1.141m 413.180us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.646m 4.172ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.646m 4.172ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.055m 12.370ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.055m 12.370ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.055m 12.370ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.055m 12.370ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.055m 12.370ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.646m 4.172ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.646m 4.172ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.800s 298.463us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.800s 298.463us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.800s 298.463us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.141m 413.180us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.055m 12.370ms 1 1 100.00
rom_ctrl_kmac_err_chk 16.490s 581.918us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.055m 12.370ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.055m 12.370ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.055m 12.370ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 21.720s 5.312ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.646m 4.172ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.600m 2.597ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00