RV_TIMER Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.470s	18.194us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.680s	16.465us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.610s	20.402us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.260s	87.692us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.720s	62.057us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.750s	26.457us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.610s	20.402us	1	1	100.00
		rv_timer_csr_aliasing	1.720s	62.057us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.620s	2.201ms	1	1	100.00
V2	disabled	rv_timer_disabled	2.090s	544.446us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.547m	242.554ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.547m	242.554ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.520s	5.849ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.420s	15.975us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.580s	33.883us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	3.360s	620.958us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	3.360s	620.958us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.680s	16.465us	1	1	100.00
		rv_timer_csr_rw	1.610s	20.402us	1	1	100.00
		rv_timer_csr_aliasing	1.720s	62.057us	1	1	100.00
		rv_timer_same_csr_outstanding	2.020s	35.991us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.680s	16.465us	1	1	100.00
		rv_timer_csr_rw	1.610s	20.402us	1	1	100.00
		rv_timer_csr_aliasing	1.720s	62.057us	1	1	100.00
		rv_timer_same_csr_outstanding	2.020s	35.991us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.650s	49.520us	1	1	100.00
		rv_timer_tl_intg_err	2.300s	777.800us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.300s	777.800us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	8.750s	1.556ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.470s	32.281us	1	1	100.00
		rv_timer_max	1.490s	18.380us	1	1	100.00
		TOTAL			19	19	100.00