SPI_DEVICE/1R1W Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	1.518m	17.039ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.940s	23.720us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.750s	77.293us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	17.630s	2.961ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	17.300s	4.759ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.750s	55.190us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.750s	77.293us	1	1	100.00
		spi_device_csr_aliasing	17.300s	4.759ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.740s	25.724us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.480s	55.290us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.650s	18.723us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.580s	1.089us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.540s	12.798us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	4.410s	265.542us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	4.410s	265.542us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	5.840s	2.713ms	1	1	100.00
		spi_device_tpm_sts_read	1.630s	98.415us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	13.040s	6.927ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	3.980s	3.842ms	1	1	100.00
		spi_device_flash_all	1.600s	21.832us	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	3.770s	561.287us	1	1	100.00
		spi_device_flash_all	1.600s	21.832us	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	3.770s	561.287us	1	1	100.00
		spi_device_flash_all	1.600s	21.832us	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.600s	21.832us	1	1	100.00
V2	cmd_read_status	spi_device_intercept	2.700s	76.557us	1	1	100.00
		spi_device_flash_all	1.600s	21.832us	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	2.700s	76.557us	1	1	100.00
		spi_device_flash_all	1.600s	21.832us	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	2.700s	76.557us	1	1	100.00
		spi_device_flash_all	1.600s	21.832us	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	2.700s	76.557us	1	1	100.00
		spi_device_flash_all	1.600s	21.832us	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	2.700s	76.557us	1	1	100.00
		spi_device_flash_all	1.600s	21.832us	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	7.530s	847.395us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	7.410s	11.934ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	7.410s	11.934ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	7.410s	11.934ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.340s	868.617us	1	1	100.00
		spi_device_read_buffer_direct	5.970s	5.769ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	7.410s	11.934ms	1	1	100.00
		spi_device_flash_all	1.600s	21.832us	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.600s	21.832us	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.600s	21.832us	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.420s	29.037us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.420s	29.037us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	1.518m	17.039ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	3.062m	136.527ms	1	1	100.00
V2	stress_all	spi_device_stress_all	2.060s	930.342us	1	1	100.00
V2	alert_test	spi_device_alert_test	1.470s	22.249us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.700s	14.552us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.690s	31.091us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.690s	31.091us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.940s	23.720us	1	1	100.00
		spi_device_csr_rw	2.750s	77.293us	1	1	100.00
		spi_device_csr_aliasing	17.300s	4.759ms	1	1	100.00
		spi_device_same_csr_outstanding	3.740s	1.183ms	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.940s	23.720us	1	1	100.00
		spi_device_csr_rw	2.750s	77.293us	1	1	100.00
		spi_device_csr_aliasing	17.300s	4.759ms	1	1	100.00
		spi_device_same_csr_outstanding	3.740s	1.183ms	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.900s	1.048ms	1	1	100.00
		spi_device_tl_intg_err	5.640s	253.757us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	5.640s	253.757us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	31.370s	23.837ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.67847113758427394520410924358138148774366097237598944906631624339901154989779
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @    909214 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[87])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @    909214 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @    909214 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[983])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.31532566442287100305016898226868420043203669640840773817241201038561044870695
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @  10518052 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7eb8cf [11111101011100011001111] vs 0x0 [0])
        UVM_ERROR @  10592052 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x39e9d1 [1110011110100111010001] vs 0x0 [0])
        UVM_ERROR @  10652052 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa1891e [101000011000100100011110] vs 0x0 [0])
        UVM_ERROR @  10672052 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x468b02 [10001101000101100000010] vs 0x0 [0])
        UVM_ERROR @  10701052 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2ee10e [1011101110000100001110] vs 0x0 [0])