SPI_HOST Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	15.000s	585.694us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	54.391us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	17.039us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	43.277us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	22.150us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	70.664us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	17.039us	1	1	100.00
		spi_host_csr_aliasing	4.000s	22.150us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	15.021us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	39.261us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	9.000s	28.366us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	11.000s	745.569us	1	1	100.00
		spi_host_error_cmd	8.000s	24.364us	1	1	100.00
		spi_host_event	4.783m	38.489ms	1	1	100.00
V2	clock_rate	spi_host_speed	12.000s	141.231us	1	1	100.00
V2	speed	spi_host_speed	12.000s	141.231us	1	1	100.00
V2	chip_select_timing	spi_host_speed	12.000s	141.231us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	10.000s	217.645us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	7.000s	32.259us	1	1	100.00
V2	cpol_cpha	spi_host_speed	12.000s	141.231us	1	1	100.00
V2	full_cycle	spi_host_speed	12.000s	141.231us	1	1	100.00
V2	duplex	spi_host_smoke	15.000s	585.694us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	15.000s	585.694us	1	1	100.00
V2	stress_all	spi_host_stress_all	15.983m	1.000s	0	1	0.00
V2	spien	spi_host_spien	5.000s	206.997us	1	1	100.00
V2	stall	spi_host_status_stall	1.033m	6.208ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	7.000s	80.628us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	11.000s	745.569us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	39.938us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	15.017us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	96.184us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	96.184us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	54.391us	1	1	100.00
		spi_host_csr_rw	4.000s	17.039us	1	1	100.00
		spi_host_csr_aliasing	4.000s	22.150us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	60.820us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	54.391us	1	1	100.00
		spi_host_csr_rw	4.000s	17.039us	1	1	100.00
		spi_host_csr_aliasing	4.000s	22.150us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	60.820us	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	934.484us	1	1	100.00
		spi_host_sec_cm	4.000s	108.334us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	934.484us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	8.750m	16.264ms	1	1	100.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_stress_all has 1 failures.

    • 0.spi_host_stress_all.33223763558579337478580854997518929480177346370932673237344591748552767211682
      Line 346, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_stress_all/latest/run.log

        UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---