SRAM_CTRL/MAIN Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	28.590s	978.255us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.620s	20.051us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.540s	16.916us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.980s	70.612us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.650s	37.650us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.640s	1.262ms	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.540s	16.916us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	37.650us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	1.719m	10.960ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.445m	6.303ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	9.273m	43.530ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.832m	6.824ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	14.605m	195.330ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	4.687m	10.324ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	46.430s	23.872ms	1	1	100.00
V2	executable	sram_ctrl_executable	2.106m	10.581ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	5.740s	714.268us	1	1	100.00
		sram_ctrl_partial_access_b2b	3.865m	50.211ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	51.060s	1.510ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	12.020s	1.459ms	1	1	100.00
		sram_ctrl_throughput_w_readback	4.110s	706.503us	1	1	100.00
V2	regwen	sram_ctrl_regwen	4.079m	41.573ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.990s	6.737ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	57.829m	491.428ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.490s	33.094us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.220s	142.749us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.220s	142.749us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.620s	20.051us	1	1	100.00
		sram_ctrl_csr_rw	1.540s	16.916us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	37.650us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.680s	27.646us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.620s	20.051us	1	1	100.00
		sram_ctrl_csr_rw	1.540s	16.916us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	37.650us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.680s	27.646us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	16.870s	3.695ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.630s	2.619us	0	1	0.00
		sram_ctrl_tl_intg_err	2.360s	635.366us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.630s	2.619us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.360s	635.366us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	4.079m	41.573ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	4.079m	41.573ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.540s	16.916us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	2.106m	10.581ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	2.106m	10.581ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	2.106m	10.581ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	46.430s	23.872ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.380s	3.509ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	16.870s	3.695ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.800s	2.740ms	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	28.590s	978.255us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	28.590s	978.255us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	2.106m	10.581ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.630s	2.619us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	46.430s	23.872ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.630s	2.619us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.630s	2.619us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	28.590s	978.255us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.630s	2.619us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.031m	1.127ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.102990733668276433785472560119967247443005526553801784870983928469928150091643
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 2740338818 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0x28) != exp (0x15)
        UVM_INFO @ 2740338818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(depth_o <= *'(Depth))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.41088444662290529289903383011221021691770517293560329184653863957354725051513
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(depth_o <= 2'(Depth))'
        UVM_ERROR @   2619235 ps: (prim_fifo_sync.sv:209) [ASSERT FAILED] depthShallNotExceedParamDepth
        UVM_INFO @   2619235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---