SRAM_CTRL/RET Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 7.880s 291.666us 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.960s 17.677us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 1.540s 32.591us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 1.980s 135.692us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.690s 42.491us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 1.690s 28.719us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.540s 32.591us 1 1 100.00
sram_ctrl_csr_aliasing 1.690s 42.491us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 9.870s 684.691us 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 4.260s 539.287us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 9.404m 18.318ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 2.821m 2.360ms 1 1 100.00
V2 bijection sram_ctrl_bijection 41.470s 889.552us 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 13.468m 4.784ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 8.190s 3.350ms 1 1 100.00
V2 executable sram_ctrl_executable 8.324m 3.169ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 13.440s 2.460ms 1 1 100.00
sram_ctrl_partial_access_b2b 4.132m 13.154ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 2.140s 172.834us 1 1 100.00
sram_ctrl_throughput_w_partial_write 43.530s 597.262us 1 1 100.00
sram_ctrl_throughput_w_readback 4.620s 86.264us 1 1 100.00
V2 regwen sram_ctrl_regwen 12.279m 3.960ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 2.000s 27.740us 1 1 100.00
V2 stress_all sram_ctrl_stress_all 24.043m 66.383ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 1.620s 42.401us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.070s 1.449ms 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.070s 1.449ms 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.960s 17.677us 1 1 100.00
sram_ctrl_csr_rw 1.540s 32.591us 1 1 100.00
sram_ctrl_csr_aliasing 1.690s 42.491us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.720s 26.136us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.960s 17.677us 1 1 100.00
sram_ctrl_csr_rw 1.540s 32.591us 1 1 100.00
sram_ctrl_csr_aliasing 1.690s 42.491us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.720s 26.136us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 3.370s 577.763us 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 1.480s 4.043us 0 1 0.00
sram_ctrl_tl_intg_err 2.310s 225.214us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 1.480s 4.043us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.310s 225.214us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 12.279m 3.960ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 12.279m 3.960ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.540s 32.591us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 8.324m 3.169ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 8.324m 3.169ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 8.324m 3.169ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 8.190s 3.350ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 1.930s 223.129us 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 3.370s 577.763us 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 2.390s 43.115us 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 7.880s 291.666us 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 7.880s 291.666us 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 8.324m 3.169ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 1.480s 4.043us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 8.190s 3.350ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 1.480s 4.043us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 1.480s 4.043us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 7.880s 291.666us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 1.480s 4.043us 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 52.860s 2.379ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets