UART Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: 86da20b

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.790s	690.799us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.520s	35.187us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.540s	22.809us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.090s	96.000us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.630s	21.286us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.810s	188.333us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.540s	22.809us	1	1	100.00
		uart_csr_aliasing	1.630s	21.286us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.299m	62.857ms	1	1	100.00
V2	parity	uart_smoke	2.790s	690.799us	1	1	100.00
		uart_tx_rx	1.299m	62.857ms	1	1	100.00
V2	parity_error	uart_intr	34.320s	68.775ms	1	1	100.00
		uart_rx_parity_err	1.937m	261.693ms	1	1	100.00
V2	watermark	uart_tx_rx	1.299m	62.857ms	1	1	100.00
		uart_intr	34.320s	68.775ms	1	1	100.00
V2	fifo_full	uart_fifo_full	30.680s	24.689ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	4.288m	193.484ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	14.290s	26.987ms	1	1	100.00
V2	rx_frame_err	uart_intr	34.320s	68.775ms	1	1	100.00
V2	rx_break_err	uart_intr	34.320s	68.775ms	1	1	100.00
V2	rx_timeout	uart_intr	34.320s	68.775ms	1	1	100.00
V2	perf	uart_perf	6.564m	11.116ms	1	1	100.00
V2	sys_loopback	uart_loopback	6.580s	5.459ms	1	1	100.00
V2	line_loopback	uart_loopback	6.580s	5.459ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	56.220s	114.070ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	6.390s	5.036ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	12.410s	12.942ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	15.300s	2.971ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	5.817m	210.885ms	1	1	100.00
V2	stress_all	uart_stress_all	10.822m	179.718ms	1	1	100.00
V2	alert_test	uart_alert_test	1.460s	41.784us	1	1	100.00
V2	intr_test	uart_intr_test	1.560s	14.801us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.990s	40.041us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.990s	40.041us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.520s	35.187us	1	1	100.00
		uart_csr_rw	1.540s	22.809us	1	1	100.00
		uart_csr_aliasing	1.630s	21.286us	1	1	100.00
		uart_same_csr_outstanding	1.750s	36.252us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.520s	35.187us	1	1	100.00
		uart_csr_rw	1.540s	22.809us	1	1	100.00
		uart_csr_aliasing	1.630s	21.286us	1	1	100.00
		uart_same_csr_outstanding	1.750s	36.252us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.630s	41.923us	1	1	100.00
		uart_tl_intg_err	1.810s	44.887us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.810s	44.887us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	14.800s	6.967ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00