CHIP Simulation Results

Monday May 12 2025 17:07:02 UTC

GitHub Revision: `86da20b`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.137m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.137m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.454m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.386m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	49.096s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.796m	5.233ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.796m	5.233ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.796m	5.233ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	39.260s	10.320us	0	1	0.00
		chip_sw_example_manufacturer	2.535m		0	1	0.00
		chip_sw_example_concurrency	4.032m	3.139ms	1	1	100.00
		chip_sw_uart_smoketest_signed	12.628s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	11.440s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	14.780s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	14.780s		0	1	0.00
V1	xbar_smoke	xbar_smoke	18.190s	56.243us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.995m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.302m	9.166ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.415m	5.804ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	35.568s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	22.841s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	55.782s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	46.229s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.650s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.650s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.411m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.166m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.747m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.747m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.126m	4.574ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.478m	5.326ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	5.154m	13.754ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.861s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.400s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	20.582m	27.159ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	6.198m	6.245ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.471m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.471m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.807s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.527m	4.634ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.527m	4.634ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.477m	18.015ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.688m	4.550ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.206m	4.025ms	1	1	100.00
		chip_sw_aes_idle	4.405m	4.065ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.218m	4.916ms	1	1	100.00
		chip_sw_kmac_idle	4.555m	4.908ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.092m	12.015ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.252m	12.026ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.901m	12.021ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	13.486m	12.016ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.308s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.836s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.723s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.694s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.154s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.644s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.077s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.308s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.836s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.723s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.694s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.154s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.644s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.077s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.757s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.210m	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	1.021m	10.100us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	47.950s	10.180us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	56.480s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.328s		0	1	0.00
		chip_sw_clkmgr_jitter	4.523m	5.577ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.198m	4.802ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.601s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	48.950s	10.180us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	1.008m	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	47.770s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	58.280s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	58.090s	10.240us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	15.408s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	13.720s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.344s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	10.567s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	18.386m	14.776ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.497m	13.962ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.527m	4.634ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	17.858s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.497m	13.962ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	25.248s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	18.760s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	26.486s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	16.494s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	17.458s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	18.386m	14.776ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	5.154m	13.754ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	23.629m	20.016ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.567m	8.334ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	7.802m	7.222ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.739m	5.405ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	18.386m	14.776ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	13.017s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.824s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	18.386m	14.776ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.820s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	7.802m	7.222ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.780s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	14.485s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	12.584s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.549s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.139s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11.669s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.824s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	24.654s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.400s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	24.654s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	24.654s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	24.654s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	9.198m	7.866ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.405s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	16.402s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	34.230s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	29.224s		0	1	0.00
		chip_sw_lc_ctrl_transition	24.654s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.530m	6.749ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.166m	13.368ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	12.627s		0	1	0.00
		chip_prim_tl_access	15.918m	23.440ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.308s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.836s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.723s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.694s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.154s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	10.644s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.077s		0	1	0.00
		chip_rv_dm_lc_disabled	20.582m	27.159ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.969m	4.342ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	1.210m	10.160us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.168m	4.882ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.405m	4.065ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.648m	3.532ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	1.021m	10.100us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.218m	4.916ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.202m	4.302ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.446m	5.466ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	56.480s	10.160us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.530m	6.749ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	24.654s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	42.570s	10.240us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.252m	4.006ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.555m	4.908ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.803s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.803s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.078s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.468m	4.274ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	12.688s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.530m	6.749ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	47.950s	10.180us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	12.285s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.757s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.206m	4.025ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.206m	4.025ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.206m	4.025ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	7.174m	4.523ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.166m	13.368ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.166m	13.368ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.638m	7.201ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.328s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	12.627s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	18.386m	14.776ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.747m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	24.654s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	7.174m	4.523ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.530m	6.749ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.638m	7.201ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.455m	4.661ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	7.174m	4.523ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.530m	6.749ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.638m	7.201ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.455m	4.661ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	24.654s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	13.311s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	19.400s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.405s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	16.402s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	34.230s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	29.224s		0	1	0.00
		chip_sw_lc_ctrl_transition	24.654s		0	1	0.00
		chip_prim_tl_access	15.918m	23.440ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	15.918m	23.440ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	12.279s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	15.830s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	13.720s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.757s		0	1	0.00
		chip_sw_aes_enc_jitter_en	1.210m	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	1.021m	10.100us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	47.950s	10.180us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	56.480s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.328s		0	1	0.00
		chip_sw_clkmgr_jitter	4.523m	5.577ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.851m	7.875ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.851m	7.875ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.286m	4.515ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.695m	4.566ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.626m	4.335ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	8.023m	6.360ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.143m	4.186ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.085m	4.725ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.455m	4.661ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	23.629m	20.016ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	23.629m	20.016ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.681m	4.638ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.726m	3.417ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.478m	4.305ms	1	1	100.00
		chip_sw_csrng_smoketest	3.232m	3.768ms	1	1	100.00
		chip_sw_gpio_smoketest	4.440m	6.104ms	1	1	100.00
		chip_sw_hmac_smoketest	4.274m	5.818ms	1	1	100.00
		chip_sw_kmac_smoketest	4.174m	4.936ms	1	1	100.00
		chip_sw_otbn_smoketest	4.638m	5.157ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.967m	5.275ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.457m	5.011ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.612m	7.106ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.621m	4.182ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.312m	5.415ms	1	1	100.00
		chip_sw_uart_smoketest	4.030m	4.948ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.299s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	12.628s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.995m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.230s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.722m	4.803ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.713m	4.271ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.426m	5.242ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.337m	5.383ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	14.685s		0	1	0.00
		chip_rv_dm_lc_disabled	20.582m	27.159ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	22.033s		0	1	0.00
		chip_sw_lc_walkthrough_prod	28.495s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	13.397s		0	1	0.00
		chip_sw_lc_walkthrough_rma	15.257s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	14.685s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	13.509s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	12.058s		0	1	0.00
		rom_volatile_raw_unlock	11.639s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	15.782s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.334m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.392m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.232m	4.771ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.232m	4.771ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	14.780s		0	1	0.00
		chip_same_csr_outstanding	12.240s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	14.780s		0	1	0.00
		chip_same_csr_outstanding	12.240s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	55.390s	46.639us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.750s	13.871us	1	1	100.00
		xbar_smoke_large_delays	4.018m	2.117ms	1	1	100.00
		xbar_smoke_slow_rsp	4.280m	1.609ms	1	1	100.00
		xbar_random_zero_delays	18.630s	17.809us	1	1	100.00
		xbar_random_large_delays	6.219m	3.295ms	1	1	100.00
		xbar_random_slow_rsp	6.878m	2.578ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	30.010s	22.226us	1	1	100.00
		xbar_error_and_unmapped_addr	58.130s	141.621us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	32.870s	73.779us	1	1	100.00
		xbar_error_and_unmapped_addr	58.130s	141.621us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.138m	725.052us	1	1	100.00
		xbar_access_same_device_slow_rsp	41.664m	16.428ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	27.650s	26.392us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	11.000m	1.671ms	1	1	100.00
		xbar_stress_all_with_error	1.876m	366.750us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	35.480m	4.462ms	1	1	100.00
		xbar_stress_all_with_reset_error	22.199m	970.926us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.076s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.407s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	13.397s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	12.351s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	13.740s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.633s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.369s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.211s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.629s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.504s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.530s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.935s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.374s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.013s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.817s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.508s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.751s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.804s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.917s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.377s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.480s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.098s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.376s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	12.047s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.148s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	11.582s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	11.372s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.840s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.089s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.734s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.106s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.487s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	11.770s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.277s		0	1	0.00
		rom_e2e_asm_init_dev	10.992s		0	1	0.00
		rom_e2e_asm_init_prod	11.789s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.231s		0	1	0.00
		rom_e2e_asm_init_rma	12.345s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.812s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.981s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.756s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	11.657s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.565m	4.822ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.126m	4.161ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.964s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.480s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.003s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.718s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	18.386m	14.776ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	11.957s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	18.699m	12.776ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	13.110s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	11.459s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.964s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.480s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.003s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.164s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.985s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.698s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	50.342s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.312m	12.315ms	1	1	100.00
		chip_plic_all_irqs_0	8.768m	5.106ms	1	1	100.00
		chip_plic_all_irqs_10	10.712m	7.341ms	1	1	100.00
		chip_sw_dma_inline_hashing	5.065m	4.170ms	1	1	100.00
		chip_sw_dma_abort	5.125m	5.787ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.005s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.839s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.936s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.960s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.306s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.278s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.300s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.841s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	12.482s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.240s		0	1	0.00
		chip_sw_mbx_smoketest	4.165m	4.166ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.29221582225453069740407261484091693574481649481102331942537285249756406607861
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (d736a7)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 136.257s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.45758592656457173826369752020270576593971550941486901747243214514257655885090
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (ff8c3d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 154.698s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.36061604128932406803989802444121474585020865786675653079629307792515166266790
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (1efc21)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 134.212s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.112473740636551579269951705584262928031287259373062684888327386812306474944599
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (fdbf92)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 118.811s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.60743801293878413949580551487628947322385364467913319344675233819678909604343
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (44379d)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 116.859s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.49693041166839271084211349189242269106687579368740833037845775681733211361349
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.46557549459799564411472570191821484263710487396894032378074499131012545248038
    Line 419, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.83638754541562842327061561703488566870249368656138751184964575710130981841839
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.31222812422649919387896881492010439162267224021614195068702729130256143323093
    Line 418, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.18789409573637405232762020418095190984583390319740012512060513371321336994820
    Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.10172462448054528206627166848716847016997025425293676611951294472154997841011
Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12014.731874 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.731874 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.31603040373402034013182598428080001988418221922772966910965483437016684506019
Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12025.686301 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12025.686301 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.113877948030001620369967222813581079448007461442232406068533106366841134759431
Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12021.155027 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12021.155027 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.106842405491956011445924961559170580056090469345379455142734163004595074764554
Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12016.317536 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.317536 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.32618917252013121061291034934427186070309102348394573399852245366801052740140
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.34542898793691909078615090805027493686388718827838320854730902769980781335497
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.45202295959926518266378195043889680384216771403950601199086414291328764547247
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.20514961803934120502542779816376073846591244531532381986671296346416945896655
Line 480, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20015.842555 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20015.842555 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.79411138589505990535606497483785645258505469920383384652859437197936278017418
Line 440, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.159249 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.159249 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.70575342790000548568408878268410857371081425196666099130736409307781504889538
Line 452, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18015.267560 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18015.267560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.54757478696289545299120017074713594694329902094372660682996321127164122330563
Line 478, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6748.649074 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (62614703521495002031837330129312317980301550433169647855504400175128143760842 [0x8a6eaa9241053ad2136d6c40c3fe2eddbd2ed0eca9b4105174f1d7fe0d348dca] vs 80991795076012368828527159346664816113995474891929314939546398774622672865728 [0xb30fbb4482f8680383d388f9852b8fdf35ff9b8683b74d8b6d804c58cc0349c0])
  UVM_INFO @ 6748.649074 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.67915681839231802679540094783017551035258659731855312285097497627395758406739
Line 484, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 7865.908452 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (75762658021316071793413957180844467105630192258761339133053118690037866992182 [0xa7802513403d211bb4e8787be18694cde4631b95b420095d3dfdc02295449236] vs 40658424219393094310690006773513580201687361556556536667772056799290220090352 [0x59e3da43eb168d0a6375d13628d948463a467304d901d7ade71b2915198013f0])
  UVM_INFO @ 7865.908452 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.18245093926142222548702660196581822780827268713947062596522248385238225767508
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4573.910080 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hdada7537  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha  a_opcode: 'h0  a_user: 'h2695b  d_param: 'h0  d_source: 'ha  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4573.910080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.98091751720513007642572192919101104289069660724038837038271914239011553330293
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5325.507198 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hda3e76ce  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h22  a_opcode: 'h0  a_user: 'h2690b  d_param: 'h0  d_source: 'h22  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5325.507198 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.110119416974981687899398660636970125307836470546134859112265072907099640811055
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.15186895300344795119144914672952397194724939241065158566257473883939433180754
    Line 452, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5804.491542 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5804.491542 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.68661233920379287629706926838895078690102940080383705205491044636311321826829
    Line 671, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 7221.798610 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 7221.798610 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.40425707569523405132692718269263011723344739220257319437240659412818345355973
    Line 459, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 4515.012152 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 4515.012152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.84571447302530650006743217940342057529002000806325537381273896361299763191358
    Line 454, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4565.920388 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4565.920388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.79970413531708675853485908120286699070742221383076446750182670901392697354310
    Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4634.235844 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4634.235844 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.72866648965736447736314318689464689915915863643765362246693442336784702226924
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6359.622656 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6359.622656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.104145637565200264983394526717029647620282522689335581947338616395430936120860
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.240001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36608) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.84147395799956688361689887058575418914186428884932387119067775624026519694863
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4770.902410 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36608) { a_addr: 'h1465112  a_data: 'h173169b  a_mask: 'h0  a_size: 'h0  a_param: 'h0  a_source: 'h40  a_opcode: 'h4  a_user: 'h279a6  d_param: 'h0  d_source: 'h40  d_data: 'h0  d_size: 'h0  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h4aa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4770.902410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.47090893228815870459663771828677837794089662712548100186330601977159652211180
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 13753.549456 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 13753.549456 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.76377406969833787350360621807850848608995261894677056881071107334742415359995
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.74900497579964592723049702437532997540401495862242140748600475447341362797207
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5786.661272 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5786.661272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```