DMA Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	1.608ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	7.000s	598.693us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	1.204ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	58.171us	1	1	100.00
V1	csr_rw	dma_csr_rw	5.000s	32.884us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	16.000s	999.465us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	459.365us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	164.104us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	5.000s	32.884us	1	1	100.00
		dma_csr_aliasing	7.000s	459.365us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	1.383m	5.990ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	5.150m	30.563ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	58.650m	348.385ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	1.967m	10.932ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	5.150m	30.563ms	1	1	100.00
V2	dma_abort	dma_abort	12.000s	3.363ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.133m	19.453ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	16.494us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	119.550us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	119.550us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	58.171us	1	1	100.00
		dma_csr_rw	5.000s	32.884us	1	1	100.00
		dma_csr_aliasing	7.000s	459.365us	1	1	100.00
		dma_same_csr_outstanding	5.000s	65.097us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	58.171us	1	1	100.00
		dma_csr_rw	5.000s	32.884us	1	1	100.00
		dma_csr_aliasing	7.000s	459.365us	1	1	100.00
		dma_same_csr_outstanding	5.000s	65.097us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	31.000s	1.396ms	1	1	100.00
		dma_generic_stress	1.967m	10.932ms	1	1	100.00
		dma_handshake_stress	5.150m	30.563ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	105.741us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	57.000s	8.418ms	1	1	100.00
		dma_longer_transfer	6.000s	1.776ms	1	1	100.00
		TOTAL			21	21	100.00