EDN Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.900s 22.406us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.890s 46.273us 1 1 100.00
V1 csr_rw edn_csr_rw 1.900s 31.023us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 2.490s 65.562us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 1.990s 20.989us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.100s 28.423us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.900s 31.023us 1 1 100.00
edn_csr_aliasing 1.990s 20.989us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 2.000s 30.323us 1 1 100.00
V2 csrng_commands edn_genbits 2.000s 30.323us 1 1 100.00
V2 genbits edn_genbits 2.000s 30.323us 1 1 100.00
V2 interrupts edn_intr 1.750s 49.433us 1 1 100.00
V2 alerts edn_alert 2.180s 30.148us 1 1 100.00
V2 errs edn_err 2.000s 119.671us 1 1 100.00
V2 disable edn_disable 1.650s 18.084us 1 1 100.00
edn_disable_auto_req_mode 2.120s 82.281us 1 1 100.00
V2 stress_all edn_stress_all 4.870s 236.329us 1 1 100.00
V2 intr_test edn_intr_test 2.200s 233.012us 1 1 100.00
V2 alert_test edn_alert_test 1.820s 113.005us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.520s 380.478us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.520s 380.478us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.890s 46.273us 1 1 100.00
edn_csr_rw 1.900s 31.023us 1 1 100.00
edn_csr_aliasing 1.990s 20.989us 1 1 100.00
edn_same_csr_outstanding 1.710s 35.492us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.890s 46.273us 1 1 100.00
edn_csr_rw 1.900s 31.023us 1 1 100.00
edn_csr_aliasing 1.990s 20.989us 1 1 100.00
edn_same_csr_outstanding 1.710s 35.492us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 5.730s 402.498us 1 1 100.00
edn_tl_intg_err 3.100s 1.107ms 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.750s 21.064us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 2.180s 30.148us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 5.730s 402.498us 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 5.730s 402.498us 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 5.730s 402.498us 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 5.730s 402.498us 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.180s 30.148us 1 1 100.00
edn_sec_cm 5.730s 402.498us 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.180s 30.148us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.100s 1.107ms 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets