HMAC Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.190s 6.163ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.820s 141.711us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.680s 73.769us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.950s 939.466us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 6.500s 155.508us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 2.960s 131.153us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.680s 73.769us 1 1 100.00
hmac_csr_aliasing 6.500s 155.508us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 57.160s 18.516ms 1 1 100.00
V2 back_pressure hmac_back_pressure 15.140s 354.615us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 10.150s 236.420us 1 1 100.00
hmac_test_sha384_vectors 19.970s 798.652us 1 1 100.00
hmac_test_sha512_vectors 6.324m 11.917ms 1 1 100.00
hmac_test_hmac256_vectors 11.080s 3.863ms 1 1 100.00
hmac_test_hmac384_vectors 8.560s 1.009ms 1 1 100.00
hmac_test_hmac512_vectors 11.410s 610.415us 1 1 100.00
V2 burst_wr hmac_burst_wr 10.240s 2.159ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 7.508m 3.324ms 1 1 100.00
V2 error hmac_error 8.320s 1.155ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 25.160s 2.965ms 1 1 100.00
V2 save_and_restore hmac_smoke 7.190s 6.163ms 1 1 100.00
hmac_long_msg 57.160s 18.516ms 1 1 100.00
hmac_back_pressure 15.140s 354.615us 1 1 100.00
hmac_datapath_stress 7.508m 3.324ms 1 1 100.00
hmac_burst_wr 10.240s 2.159ms 1 1 100.00
hmac_stress_all 26.915m 198.170ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.190s 6.163ms 1 1 100.00
hmac_long_msg 57.160s 18.516ms 1 1 100.00
hmac_back_pressure 15.140s 354.615us 1 1 100.00
hmac_datapath_stress 7.508m 3.324ms 1 1 100.00
hmac_wipe_secret 25.160s 2.965ms 1 1 100.00
hmac_test_sha256_vectors 10.150s 236.420us 1 1 100.00
hmac_test_sha384_vectors 19.970s 798.652us 1 1 100.00
hmac_test_sha512_vectors 6.324m 11.917ms 1 1 100.00
hmac_test_hmac256_vectors 11.080s 3.863ms 1 1 100.00
hmac_test_hmac384_vectors 8.560s 1.009ms 1 1 100.00
hmac_test_hmac512_vectors 11.410s 610.415us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.190s 6.163ms 1 1 100.00
hmac_long_msg 57.160s 18.516ms 1 1 100.00
hmac_back_pressure 15.140s 354.615us 1 1 100.00
hmac_datapath_stress 7.508m 3.324ms 1 1 100.00
hmac_burst_wr 10.240s 2.159ms 1 1 100.00
hmac_error 8.320s 1.155ms 1 1 100.00
hmac_wipe_secret 25.160s 2.965ms 1 1 100.00
hmac_test_sha256_vectors 10.150s 236.420us 1 1 100.00
hmac_test_sha384_vectors 19.970s 798.652us 1 1 100.00
hmac_test_sha512_vectors 6.324m 11.917ms 1 1 100.00
hmac_test_hmac256_vectors 11.080s 3.863ms 1 1 100.00
hmac_test_hmac384_vectors 8.560s 1.009ms 1 1 100.00
hmac_test_hmac512_vectors 11.410s 610.415us 1 1 100.00
hmac_stress_all 26.915m 198.170ms 1 1 100.00
V2 stress_all hmac_stress_all 26.915m 198.170ms 1 1 100.00
V2 alert_test hmac_alert_test 1.410s 15.985us 1 1 100.00
V2 intr_test hmac_intr_test 1.520s 12.628us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.740s 261.436us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.740s 261.436us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.820s 141.711us 1 1 100.00
hmac_csr_rw 1.680s 73.769us 1 1 100.00
hmac_csr_aliasing 6.500s 155.508us 1 1 100.00
hmac_same_csr_outstanding 2.900s 116.784us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.820s 141.711us 1 1 100.00
hmac_csr_rw 1.680s 73.769us 1 1 100.00
hmac_csr_aliasing 6.500s 155.508us 1 1 100.00
hmac_same_csr_outstanding 2.900s 116.784us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.470s 1.288ms 1 1 100.00
hmac_tl_intg_err 4.090s 1.919ms 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.090s 1.919ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.190s 6.163ms 1 1 100.00
V3 stress_reset hmac_stress_reset 1.900s 755.513us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 4.223m 7.985ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.740s 696.613us 1 1 100.00
TOTAL 28 28 100.00