I2C Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	19.870s	6.978ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.100s	2.242ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.630s	56.428us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.650s	54.073us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.030s	268.212us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.840s	67.419us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.790s	34.516us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.650s	54.073us	1	1	100.00
		i2c_csr_aliasing	1.840s	67.419us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.270s	53.630us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	1.790m	17.833ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	18.730s	2.962ms	1	1	100.00
V2	host_override	i2c_host_override	1.450s	46.938us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.807m	5.361ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.268m	1.795ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.710s	189.599us	1	1	100.00
		i2c_host_fifo_fmt_empty	13.060s	388.425us	1	1	100.00
		i2c_host_fifo_reset_rx	4.580s	902.131us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	58.330s	11.679ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	19.670s	2.885ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.500s	110.633us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.880s	8.411ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	21.030s	31.984ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.960s	3.299ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	12.230s	2.269ms	1	1	100.00
		i2c_target_intr_smoke	4.160s	1.631ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.850s	559.901us	1	1	100.00
		i2c_target_fifo_reset_tx	2.050s	255.594us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	3.130s	18.383ms	1	1	100.00
		i2c_target_stress_rd	12.230s	2.269ms	1	1	100.00
		i2c_target_intr_stress_wr	3.569m	19.847ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.750s	15.001ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	9.610s	2.447ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	6.070s	4.730ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	13.550s	10.309ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.910s	1.139ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.950s	1.131ms	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	18.730s	2.962ms	1	1	100.00
		i2c_host_perf_precise	6.290s	6.604ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	19.670s	2.885ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.730s	117.630us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.740s	491.172us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.710s	1.673ms	1	1	100.00
		i2c_target_nack_txstretch	2.650s	188.328us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.010s	1.107ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.610s	1.442ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.490s	25.421us	1	1	100.00
V2	intr_test	i2c_intr_test	1.620s	14.652us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.350s	92.512us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.350s	92.512us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.630s	56.428us	1	1	100.00
		i2c_csr_rw	1.650s	54.073us	1	1	100.00
		i2c_csr_aliasing	1.840s	67.419us	1	1	100.00
		i2c_same_csr_outstanding	1.740s	23.854us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.630s	56.428us	1	1	100.00
		i2c_csr_rw	1.650s	54.073us	1	1	100.00
		i2c_csr_aliasing	1.840s	67.419us	1	1	100.00
		i2c_same_csr_outstanding	1.740s	23.854us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.590s	129.933us	1	1	100.00
		i2c_sec_cm	1.760s	565.632us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.590s	129.933us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	29.920s	4.048ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.810s	49.863us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	17.810s	2.037ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.97782803787803668384390116884857338054446009990137825126143917014746776136568
      Line 92, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4047721191 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 4047721191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.28036548018344684119399629692396157687934114457877699739662130462841753465832
      Line 121, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2036645550 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2036645550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.70794836651867212049799426010649378454985576368865511739602008283825637455060
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @  49863018 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 55 [0x37])
        UVM_INFO @  49863018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.35755613246015289261887733571670133324805630968228627607657592482390525732636
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10309453087 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10309453087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.61025469384093787211898683593597520972558327155460725794760959185460466884700
      Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 110632889 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @32971
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.39031476433107976142516950214298950558004380925565423583789598991278413784704
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 188328053 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 188328053 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---