KEYMGR Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	5.380s	511.539us	1	1	100.00
V1	random	keymgr_random	50.420s	8.330ms	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.780s	41.297us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.850s	32.370us	0	1	0.00
V1	csr_bit_bash	keymgr_csr_bit_bash	9.990s	3.432ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	6.120s	208.567us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	1.990s	103.536us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.850s	32.370us	0	1	0.00
		keymgr_csr_aliasing	6.120s	208.567us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	7.460s	717.228us	1	1	100.00
V2	sideload	keymgr_sideload	4.350s	184.929us	1	1	100.00
		keymgr_sideload_kmac	4.840s	170.370us	1	1	100.00
		keymgr_sideload_aes	3.770s	352.609us	1	1	100.00
		keymgr_sideload_otbn	2.590s	65.084us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.820s	78.328us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.430s	164.012us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.400s	92.531us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	2.860s	137.118us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.090s	296.967us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.780s	94.238us	1	1	100.00
V2	stress_all	keymgr_stress_all	29.420s	2.192ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.680s	11.038us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.800s	44.533us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.760s	105.665us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.760s	105.665us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.780s	41.297us	1	1	100.00
		keymgr_csr_rw	1.850s	32.370us	0	1	0.00
		keymgr_csr_aliasing	6.120s	208.567us	1	1	100.00
		keymgr_same_csr_outstanding	3.300s	194.246us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.780s	41.297us	1	1	100.00
		keymgr_csr_rw	1.850s	32.370us	0	1	0.00
		keymgr_csr_aliasing	6.120s	208.567us	1	1	100.00
		keymgr_same_csr_outstanding	3.300s	194.246us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	10.660s	3.940ms	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	10.660s	3.940ms	1	1	100.00
		keymgr_tl_intg_err	2.550s	22.316us	0	1	0.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	2.140s	384.344us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	2.140s	384.344us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	2.140s	384.344us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	2.140s	384.344us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	4.940s	228.058us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	10.660s	3.940ms	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	10.660s	3.940ms	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	2.550s	22.316us	0	1	0.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	2.140s	384.344us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	7.460s	717.228us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	50.420s	8.330ms	1	1	100.00
		keymgr_csr_rw	1.850s	32.370us	0	1	0.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	50.420s	8.330ms	1	1	100.00
		keymgr_csr_rw	1.850s	32.370us	0	1	0.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	50.420s	8.330ms	1	1	100.00
		keymgr_csr_rw	1.850s	32.370us	0	1	0.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.430s	164.012us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.090s	296.967us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.090s	296.967us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	50.420s	8.330ms	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	6.340s	422.102us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	10.660s	3.940ms	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	10.660s	3.940ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	10.660s	3.940ms	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.670s	167.561us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.430s	164.012us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	10.660s	3.940ms	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	10.660s	3.940ms	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	10.660s	3.940ms	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.670s	167.561us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.670s	167.561us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	10.660s	3.940ms	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.670s	167.561us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	10.660s	3.940ms	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.670s	167.561us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	12.010s	2.006ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			28	30	93.33

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test keymgr_tl_intg_err has 1 failures.

    • 0.keymgr_tl_intg_err.107883530325861708504098404676969403826578823740491500964053899606281708353519
      Line 97, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
        UVM_ERROR @  22315560 ps: (keymgr_csr_assert_fpv.sv:456) [ASSERT FAILED] attest_sw_binding_5_rd_A
        UVM_INFO @  22315560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_rw has 1 failures.

    • 0.keymgr_csr_rw.73435486349074072594558353436173588383892351573698783444753739556018663510473
      Line 77, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[17] & 'hffffffff)))'
        UVM_ERROR @  32370163 ps: (keymgr_csr_assert_fpv.sv:451) [ASSERT FAILED] attest_sw_binding_4_rd_A
        UVM_INFO @  32370163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---