| V1 |
smoke |
keymgr_dpe_smoke |
14.050s |
2.483ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
2.050s |
104.261us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
2.090s |
72.657us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
7.600s |
595.696us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
4.730s |
412.301us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.870s |
99.911us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
2.090s |
72.657us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.730s |
412.301us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.820s |
13.533us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.800s |
20.689us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
3.820s |
118.791us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
3.820s |
118.791us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
2.050s |
104.261us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
2.090s |
72.657us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.730s |
412.301us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.310s |
46.474us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
2.050s |
104.261us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
2.090s |
72.657us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.730s |
412.301us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.310s |
46.474us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
4.690s |
351.160us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
4.380s |
325.862us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
3.060s |
78.057us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
3.060s |
78.057us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
3.060s |
78.057us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
3.060s |
78.057us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
4.410s |
490.511us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
4.690s |
351.160us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
4.690s |
351.160us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |