| V1 |
smoke |
kmac_smoke |
30.120s |
2.969ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
kmac_csr_hw_reset |
1.840s |
21.300us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
kmac_csr_rw |
1.920s |
101.096us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
kmac_csr_bit_bash |
6.270s |
154.393us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
kmac_csr_aliasing |
5.810s |
269.177us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
kmac_csr_mem_rw_with_rand_reset |
2.560s |
83.080us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
kmac_csr_rw |
1.920s |
101.096us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.810s |
269.177us |
1 |
1 |
100.00 |
| V1 |
mem_walk |
kmac_mem_walk |
1.670s |
34.664us |
1 |
1 |
100.00 |
| V1 |
mem_partial_access |
kmac_mem_partial_access |
2.180s |
31.478us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2 |
long_msg_and_output |
kmac_long_msg_and_output |
13.570m |
9.828ms |
1 |
1 |
100.00 |
| V2 |
burst_write |
kmac_burst_write |
16.828m |
103.288ms |
1 |
1 |
100.00 |
| V2 |
test_vectors |
kmac_test_vectors_sha3_224 |
32.376m |
188.264ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_256 |
35.880s |
15.223ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_384 |
24.725m |
68.606ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_sha3_512 |
16.883m |
311.497ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_128 |
3.141m |
57.055ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_shake_256 |
5.275m |
87.831ms |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac |
3.400s |
119.905us |
1 |
1 |
100.00 |
|
|
kmac_test_vectors_kmac_xof |
3.700s |
371.094us |
1 |
1 |
100.00 |
| V2 |
sideload |
kmac_sideload |
3.287m |
68.937ms |
1 |
1 |
100.00 |
| V2 |
app |
kmac_app |
4.384m |
21.714ms |
1 |
1 |
100.00 |
| V2 |
app_with_partial_data |
kmac_app_with_partial_data |
3.235m |
45.354ms |
1 |
1 |
100.00 |
| V2 |
entropy_refresh |
kmac_entropy_refresh |
1.747m |
15.403ms |
1 |
1 |
100.00 |
| V2 |
error |
kmac_error |
4.861m |
23.245ms |
1 |
1 |
100.00 |
| V2 |
key_error |
kmac_key_error |
10.730s |
22.777ms |
1 |
1 |
100.00 |
| V2 |
sideload_invalid |
kmac_sideload_invalid |
3.620s |
70.961us |
1 |
1 |
100.00 |
| V2 |
edn_timeout_error |
kmac_edn_timeout_error |
30.850s |
1.343ms |
1 |
1 |
100.00 |
| V2 |
entropy_mode_error |
kmac_entropy_mode_error |
2.340s |
142.731us |
1 |
1 |
100.00 |
| V2 |
entropy_ready_error |
kmac_entropy_ready_error |
46.060s |
5.854ms |
1 |
1 |
100.00 |
| V2 |
lc_escalation |
kmac_lc_escalation |
2.220s |
40.149us |
1 |
1 |
100.00 |
| V2 |
stress_all |
kmac_stress_all |
3.786m |
82.184ms |
1 |
1 |
100.00 |
| V2 |
intr_test |
kmac_intr_test |
1.470s |
30.921us |
1 |
1 |
100.00 |
| V2 |
alert_test |
kmac_alert_test |
1.780s |
26.332us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
kmac_tl_errors |
2.460s |
236.432us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
kmac_tl_errors |
2.460s |
236.432us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
kmac_csr_hw_reset |
1.840s |
21.300us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.920s |
101.096us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.810s |
269.177us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
3.010s |
134.675us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
kmac_csr_hw_reset |
1.840s |
21.300us |
1 |
1 |
100.00 |
|
|
kmac_csr_rw |
1.920s |
101.096us |
1 |
1 |
100.00 |
|
|
kmac_csr_aliasing |
5.810s |
269.177us |
1 |
1 |
100.00 |
|
|
kmac_same_csr_outstanding |
3.010s |
134.675us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
26 |
26 |
100.00 |
| V2S |
shadow_reg_update_error |
kmac_shadow_reg_errors |
2.600s |
160.203us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
kmac_shadow_reg_errors |
2.600s |
160.203us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
kmac_shadow_reg_errors |
2.600s |
160.203us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
kmac_shadow_reg_errors |
2.600s |
160.203us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
kmac_shadow_reg_errors_with_csr_rw |
4.440s |
238.488us |
1 |
1 |
100.00 |
| V2S |
tl_intg_err |
kmac_sec_cm |
59.680s |
18.791ms |
1 |
1 |
100.00 |
|
|
kmac_tl_intg_err |
3.820s |
365.002us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
kmac_tl_intg_err |
3.820s |
365.002us |
1 |
1 |
100.00 |
| V2S |
sec_cm_lc_escalate_en_intersig_mubi |
kmac_lc_escalation |
2.220s |
40.149us |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_key_key_masking |
kmac_smoke |
30.120s |
2.969ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_key_sideload |
kmac_sideload |
3.287m |
68.937ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_shadow |
kmac_shadow_reg_errors |
2.600s |
160.203us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_sparse |
kmac_sec_cm |
59.680s |
18.791ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_ctr_redun |
kmac_sec_cm |
59.680s |
18.791ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_packer_ctr_redun |
kmac_sec_cm |
59.680s |
18.791ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_cfg_shadowed_config_regwen |
kmac_smoke |
30.120s |
2.969ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_global_esc |
kmac_lc_escalation |
2.220s |
40.149us |
1 |
1 |
100.00 |
| V2S |
sec_cm_fsm_local_esc |
kmac_sec_cm |
59.680s |
18.791ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_absorbed_ctrl_mubi |
kmac_mubi |
27.830s |
1.142ms |
1 |
1 |
100.00 |
| V2S |
sec_cm_sw_cmd_ctrl_sparse |
kmac_smoke |
30.120s |
2.969ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
5 |
5 |
100.00 |
| V3 |
stress_all_with_rand_reset |
kmac_stress_all_with_rand_reset |
1.154m |
3.264ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
1 |
1 |
100.00 |
|
|
TOTAL |
|
|
40 |
40 |
100.00 |