KMAC/UNMASKED Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	5.470s	111.159us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.790s	114.238us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.810s	28.671us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	14.480s	3.019ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.290s	745.567us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.060s	138.054us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.810s	28.671us	1	1	100.00
		kmac_csr_aliasing	7.290s	745.567us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.590s	27.644us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.160s	43.167us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	2.762m	10.123ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.322m	100.988ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	33.720s	2.707ms	1	1	100.00
		kmac_test_vectors_sha3_256	24.240s	2.319ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.308m	73.072ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.800s	1.089ms	1	1	100.00
		kmac_test_vectors_shake_128	2.178m	17.290ms	1	1	100.00
		kmac_test_vectors_shake_256	1.581m	7.213ms	1	1	100.00
		kmac_test_vectors_kmac	3.480s	84.115us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.020s	150.232us	1	1	100.00
V2	sideload	kmac_sideload	1.866m	7.690ms	1	1	100.00
V2	app	kmac_app	2.048m	9.099ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.441m	10.683ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	3.519m	16.529ms	1	1	100.00
V2	error	kmac_error	34.870s	2.178ms	1	1	100.00
V2	key_error	kmac_key_error	4.730s	2.047ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.290s	104.817us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	23.070s	1.779ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	8.940s	1.958ms	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	10.990s	2.682ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.520s	116.245us	1	1	100.00
V2	stress_all	kmac_stress_all	2.477m	9.276ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.550s	32.186us	1	1	100.00
V2	alert_test	kmac_alert_test	1.820s	16.920us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.630s	228.818us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.630s	228.818us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.790s	114.238us	1	1	100.00
		kmac_csr_rw	1.810s	28.671us	1	1	100.00
		kmac_csr_aliasing	7.290s	745.567us	1	1	100.00
		kmac_same_csr_outstanding	1.980s	22.658us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.790s	114.238us	1	1	100.00
		kmac_csr_rw	1.810s	28.671us	1	1	100.00
		kmac_csr_aliasing	7.290s	745.567us	1	1	100.00
		kmac_same_csr_outstanding	1.980s	22.658us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	1.970s	56.498us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	1.970s	56.498us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	1.970s	56.498us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	1.970s	56.498us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.910s	56.521us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	37.570s	16.497ms	1	1	100.00
		kmac_tl_intg_err	1.940s	44.878us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.940s	44.878us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.520s	116.245us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	5.470s	111.159us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.866m	7.690ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	1.970s	56.498us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	37.570s	16.497ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	37.570s	16.497ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	37.570s	16.497ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	5.470s	111.159us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.520s	116.245us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	37.570s	16.497ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	34.670s	731.886us	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	5.470s	111.159us	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	2.368m	3.191ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			38	40	95.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.32456494218367407396225905628649636400635515922680455530042484876292622206473
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[46] & 'hffffffff)))'
        UVM_ERROR @  56520846 ps: (kmac_csr_assert_fpv.sv:527) [ASSERT FAILED] prefix_7_rd_A
        UVM_INFO @  56520846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.96865348612877739636004122367108953291989600173062079441876028226412011058451
      Line 75, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
        UVM_ERROR @  44878341 ps: (kmac_csr_assert_fpv.sv:502) [ASSERT FAILED] prefix_2_rd_A
        UVM_INFO @  44878341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---