OTBN Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	11.000s	242.990us	1	1	100.00
V1	single_binary	otbn_single	7.000s	32.969us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	7.000s	58.388us	1	1	100.00
V1	csr_rw	otbn_csr_rw	6.000s	16.005us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	9.000s	265.618us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	33.598us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	7.000s	52.226us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	6.000s	16.005us	1	1	100.00
		otbn_csr_aliasing	6.000s	33.598us	1	1	100.00
V1	mem_walk	otbn_mem_walk	29.000s	1.857ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	18.000s	131.958us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	27.000s	443.602us	1	1	100.00
V2	multi_error	otbn_multi_err	1.083m	273.591us	1	1	100.00
V2	back_to_back	otbn_multi	40.000s	137.077us	1	1	100.00
V2	stress_all	otbn_stress_all	1.033m	313.020us	1	1	100.00
V2	lc_escalation	otbn_escalate	14.000s	123.975us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	42.041us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	18.000s	58.295us	1	1	100.00
V2	alert_test	otbn_alert_test	10.000s	36.985us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	52.169us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	7.000s	210.745us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	7.000s	210.745us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	7.000s	58.388us	1	1	100.00
		otbn_csr_rw	6.000s	16.005us	1	1	100.00
		otbn_csr_aliasing	6.000s	33.598us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	29.363us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	7.000s	58.388us	1	1	100.00
		otbn_csr_rw	6.000s	16.005us	1	1	100.00
		otbn_csr_aliasing	6.000s	33.598us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	29.363us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	10.000s	24.202us	1	1	100.00
		otbn_dmem_err	10.000s	16.910us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	14.000s	23.010us	1	1	100.00
		otbn_controller_ispr_rdata_err	8.000s	80.373us	1	1	100.00
		otbn_mac_bignum_acc_err	13.000s	108.174us	1	1	100.00
		otbn_urnd_err	11.000s	24.238us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	18.258us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	39.593us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	7.000s	143.198us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	1.900m	561.914us	1	1	100.00
		otbn_tl_intg_err	1.250m	481.084us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	20.000s	109.641us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	1.900m	561.914us	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	1.900m	561.914us	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	11.000s	242.990us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	10.000s	16.910us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	10.000s	24.202us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	1.250m	481.084us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	14.000s	123.975us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	10.000s	24.202us	1	1	100.00
		otbn_dmem_err	10.000s	16.910us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	42.041us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	18.258us	1	1	100.00
		otbn_sec_cm	1.900m	561.914us	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1.900m	561.914us	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	7.000s	32.969us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	10.000s	24.202us	1	1	100.00
		otbn_dmem_err	10.000s	16.910us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	42.041us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	18.258us	1	1	100.00
		otbn_sec_cm	1.900m	561.914us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1.900m	561.914us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	14.000s	123.975us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	10.000s	24.202us	1	1	100.00
		otbn_dmem_err	10.000s	16.910us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	42.041us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	18.258us	1	1	100.00
		otbn_sec_cm	1.900m	561.914us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1.900m	561.914us	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	7.000s	32.969us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	15.000s	46.820us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	45.558us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	21.000s	64.815us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	21.000s	64.815us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	10.000s	63.341us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1.900m	561.914us	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1.900m	561.914us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	10.000s	286.474us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1.900m	561.914us	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1.900m	561.914us	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	50.421us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	20.000s	50.421us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	13.000s	25.007us	0	1	0.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	7.000s	32.969us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	7.000s	32.969us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	7.000s	32.969us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	40.000s	137.077us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	7.000s	32.969us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	7.000s	32.969us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	8.000s	76.897us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	7.000s	32.969us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1.900m	561.914us	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	3.550m	3.968ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Failure Buckets

• UVM_FATAL (otbn_base_vseq.sv:348) [otbn_dmem_err_vseq] Check failed (!cfg.under_reset) has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.49477758196459416535151474615997105481881313534865123339535121504670795359958
      Line 328, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @ 3967907991 ps: (otbn_base_vseq.sv:348) [uvm_test_top.env.virtual_sequencer.otbn_dmem_err_vseq] Check failed (!cfg.under_reset)
        UVM_INFO @ 3967907991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed has 1 failures:

  • Test otbn_sec_wipe_err has 1 failures.

    • 0.otbn_sec_wipe_err.30410239596122318420648115852491206390135446647716438239347981062365438124935
      Line 107, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_sec_wipe_err/latest/run.log

        xmsim: *E,ASRTST (/nightly/runs/scratch/master/otbn-sim-xcelium/default/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 25006970 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
        UVM_ERROR @  25006970 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
        UVM_INFO @  25006970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---