ROM_CTRL/32KB Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 4.770s 143.326us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.050s 738.541us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.740s 241.543us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.640s 539.151us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.950s 207.679us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 4.620s 421.642us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.740s 241.543us 1 1 100.00
rom_ctrl_csr_aliasing 4.950s 207.679us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.390s 602.036us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.730s 164.291us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.870s 572.244us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 13.830s 412.645us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 8.310s 1.087ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 4.840s 164.447us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 5.680s 129.161us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 5.680s 129.161us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.050s 738.541us 1 1 100.00
rom_ctrl_csr_rw 4.740s 241.543us 1 1 100.00
rom_ctrl_csr_aliasing 4.950s 207.679us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.200s 213.725us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.050s 738.541us 1 1 100.00
rom_ctrl_csr_rw 4.740s 241.543us 1 1 100.00
rom_ctrl_csr_aliasing 4.950s 207.679us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.200s 213.725us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 51.550s 1.589ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 21.690s 858.862us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.894m 4.393ms 1 1 100.00
rom_ctrl_tl_intg_err 21.470s 2.314ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.894m 4.393ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.894m 4.393ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 51.550s 1.589ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 51.550s 1.589ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 51.550s 1.589ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 51.550s 1.589ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 51.550s 1.589ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.894m 4.393ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.894m 4.393ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 4.770s 143.326us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 4.770s 143.326us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 4.770s 143.326us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 21.470s 2.314ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 51.550s 1.589ms 1 1 100.00
rom_ctrl_kmac_err_chk 8.310s 1.087ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 51.550s 1.589ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 51.550s 1.589ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 51.550s 1.589ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 21.690s 858.862us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.894m 4.393ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 3.291m 3.183ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00