ROM_CTRL/64KB Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.790s 326.632us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.660s 553.472us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.690s 214.359us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.420s 220.255us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 6.820s 3.129ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 8.470s 313.486us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.690s 214.359us 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 3.129ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 6.740s 1.034ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.420s 297.772us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.110s 732.873us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 23.160s 8.457ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 14.540s 547.712us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.840s 673.842us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.250s 370.386us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.250s 370.386us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.660s 553.472us 1 1 100.00
rom_ctrl_csr_rw 6.690s 214.359us 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 3.129ms 1 1 100.00
rom_ctrl_same_csr_outstanding 6.920s 518.841us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.660s 553.472us 1 1 100.00
rom_ctrl_csr_rw 6.690s 214.359us 1 1 100.00
rom_ctrl_csr_aliasing 6.820s 3.129ms 1 1 100.00
rom_ctrl_same_csr_outstanding 6.920s 518.841us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.198m 18.818ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 25.650s 4.280ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.598m 609.537us 1 1 100.00
rom_ctrl_tl_intg_err 38.540s 359.021us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.598m 609.537us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.598m 609.537us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.198m 18.818ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.198m 18.818ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.198m 18.818ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.198m 18.818ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.198m 18.818ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.598m 609.537us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.598m 609.537us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.790s 326.632us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.790s 326.632us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.790s 326.632us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 38.540s 359.021us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.198m 18.818ms 1 1 100.00
rom_ctrl_kmac_err_chk 14.540s 547.712us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.198m 18.818ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.198m 18.818ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.198m 18.818ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 25.650s 4.280ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.598m 609.537us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 24.280s 1.635ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00