RV_TIMER Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.640s	18.064us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.420s	51.285us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.560s	24.213us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.990s	143.836us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.450s	105.031us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.750s	30.514us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.560s	24.213us	1	1	100.00
		rv_timer_csr_aliasing	1.450s	105.031us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.490s	199.081us	1	1	100.00
V2	disabled	rv_timer_disabled	1.470s	68.870us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	52.260s	39.880ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	52.260s	39.880ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.170s	520.424us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.790s	14.386us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.540s	37.718us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.170s	328.250us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.170s	328.250us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.420s	51.285us	1	1	100.00
		rv_timer_csr_rw	1.560s	24.213us	1	1	100.00
		rv_timer_csr_aliasing	1.450s	105.031us	1	1	100.00
		rv_timer_same_csr_outstanding	1.720s	30.562us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.420s	51.285us	1	1	100.00
		rv_timer_csr_rw	1.560s	24.213us	1	1	100.00
		rv_timer_csr_aliasing	1.450s	105.031us	1	1	100.00
		rv_timer_same_csr_outstanding	1.720s	30.562us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.740s	243.585us	1	1	100.00
		rv_timer_tl_intg_err	1.770s	213.535us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	1.770s	213.535us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	20.210s	34.580ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.790s	18.586us	1	1	100.00
		rv_timer_max	1.820s	13.005us	1	1	100.00
		TOTAL			19	19	100.00