SPI_DEVICE/1R1W Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.099m	21.437ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.960s	52.429us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.220s	33.471us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	15.400s	1.128ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.940s	1.235ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.240s	52.336us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.220s	33.471us	1	1	100.00
		spi_device_csr_aliasing	16.940s	1.235ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.820s	11.571us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.780s	218.606us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.740s	20.633us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.730s	1.315us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.740s	4.810us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.750s	48.333us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.750s	48.333us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	8.490s	17.216ms	1	1	100.00
		spi_device_tpm_sts_read	1.860s	12.673us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	15.350s	3.064ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	8.170s	9.548ms	1	1	100.00
		spi_device_flash_all	29.860s	4.398ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	6.020s	6.009ms	1	1	100.00
		spi_device_flash_all	29.860s	4.398ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	6.020s	6.009ms	1	1	100.00
		spi_device_flash_all	29.860s	4.398ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	29.860s	4.398ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	24.970s	4.002ms	1	1	100.00
		spi_device_flash_all	29.860s	4.398ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	24.970s	4.002ms	1	1	100.00
		spi_device_flash_all	29.860s	4.398ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	24.970s	4.002ms	1	1	100.00
		spi_device_flash_all	29.860s	4.398ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	24.970s	4.002ms	1	1	100.00
		spi_device_flash_all	29.860s	4.398ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	24.970s	4.002ms	1	1	100.00
		spi_device_flash_all	29.860s	4.398ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	2.920s	838.109us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.880s	3.473ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.880s	3.473ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.880s	3.473ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.490s	168.366us	1	1	100.00
		spi_device_read_buffer_direct	15.010s	18.516ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.880s	3.473ms	1	1	100.00
		spi_device_flash_all	29.860s	4.398ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	29.860s	4.398ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	29.860s	4.398ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	8.620s	993.016us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	8.620s	993.016us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.099m	21.437ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.800m	66.609ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.981m	41.831ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.730s	41.592us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.950s	51.817us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.010s	42.394us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.010s	42.394us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.960s	52.429us	1	1	100.00
		spi_device_csr_rw	2.220s	33.471us	1	1	100.00
		spi_device_csr_aliasing	16.940s	1.235ms	1	1	100.00
		spi_device_same_csr_outstanding	2.470s	83.033us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.960s	52.429us	1	1	100.00
		spi_device_csr_rw	2.220s	33.471us	1	1	100.00
		spi_device_csr_aliasing	16.940s	1.235ms	1	1	100.00
		spi_device_same_csr_outstanding	2.470s	83.033us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.070s	64.197us	1	1	100.00
		spi_device_tl_intg_err	12.120s	1.292ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.120s	1.292ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	55.530s	13.657ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.33149646589464750952018512624457164884886380389628460585559759069123930272302
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1035718 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[59])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1035718 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1035718 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[955])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.80166878025158678733061441616541419472514390774776700572735491141081643932145
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1950429 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6701ec [11001110000000111101100] vs 0x0 [0])
        UVM_ERROR @   1996429 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xeae3f5 [111010101110001111110101] vs 0x0 [0])
        UVM_ERROR @   2094429 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x12695c [100100110100101011100] vs 0x0 [0])
        UVM_ERROR @   2165429 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc16b4 [11000001011010110100] vs 0x0 [0])
        UVM_ERROR @   2264429 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe7a112 [111001111010000100010010] vs 0x0 [0])