SPI_HOST Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	35.000s	3.788ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	20.122us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	26.773us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	58.848us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	30.013us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	87.125us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	26.773us	1	1	100.00
		spi_host_csr_aliasing	5.000s	30.013us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	39.878us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	15.754us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	32.799us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	6.000s	54.442us	1	1	100.00
		spi_host_error_cmd	4.000s	21.679us	1	1	100.00
		spi_host_event	36.000s	1.185ms	1	1	100.00
V2	clock_rate	spi_host_speed	5.000s	169.779us	1	1	100.00
V2	speed	spi_host_speed	5.000s	169.779us	1	1	100.00
V2	chip_select_timing	spi_host_speed	5.000s	169.779us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	53.000s	3.963ms	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	47.948us	1	1	100.00
V2	cpol_cpha	spi_host_speed	5.000s	169.779us	1	1	100.00
V2	full_cycle	spi_host_speed	5.000s	169.779us	1	1	100.00
V2	duplex	spi_host_smoke	35.000s	3.788ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	35.000s	3.788ms	1	1	100.00
V2	stress_all	spi_host_stress_all	1.583m	3.137ms	1	1	100.00
V2	spien	spi_host_spien	5.000s	854.721us	1	1	100.00
V2	stall	spi_host_status_stall	15.000s	365.429us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	80.553us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	6.000s	54.442us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	41.745us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	19.980us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	61.778us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	61.778us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	20.122us	1	1	100.00
		spi_host_csr_rw	4.000s	26.773us	1	1	100.00
		spi_host_csr_aliasing	5.000s	30.013us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	31.681us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	20.122us	1	1	100.00
		spi_host_csr_rw	4.000s	26.773us	1	1	100.00
		spi_host_csr_aliasing	5.000s	30.013us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	31.681us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	113.179us	1	1	100.00
		spi_host_sec_cm	4.000s	455.951us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	113.179us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	3.150m	7.155ms	1	1	100.00
		TOTAL			26	26	100.00