SRAM_CTRL/MAIN Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	14.000s	2.795ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.640s	23.503us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.590s	37.430us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.150s	320.688us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.630s	16.179us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.270s	704.877us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.590s	37.430us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	16.179us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.646m	14.413ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.567m	6.297ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	11.609m	20.362ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.145m	8.656ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	27.406m	132.512ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	8.452m	30.291ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	26.420s	6.893ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.890m	4.755ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	46.110s	6.097ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.545m	26.079ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.221m	5.449ms	1	1	100.00
		sram_ctrl_throughput_w_partial_write	7.400s	2.770ms	1	1	100.00
		sram_ctrl_throughput_w_readback	9.080s	1.397ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	9.199m	9.516ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	5.460s	1.342ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	14.476m	31.703ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.910s	22.953us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.480s	589.594us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.480s	589.594us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.640s	23.503us	1	1	100.00
		sram_ctrl_csr_rw	1.590s	37.430us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	16.179us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	38.752us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.640s	23.503us	1	1	100.00
		sram_ctrl_csr_rw	1.590s	37.430us	1	1	100.00
		sram_ctrl_csr_aliasing	1.630s	16.179us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.580s	38.752us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	18.930s	24.540ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.780s	5.462us	0	1	0.00
		sram_ctrl_tl_intg_err	2.950s	278.899us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.780s	5.462us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.950s	278.899us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	9.199m	9.516ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	9.199m	9.516ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.590s	37.430us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.890m	4.755ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.890m	4.755ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.890m	4.755ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	26.420s	6.893ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	5.120s	2.812ms	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	18.930s	24.540ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	5.450s	660.284us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	14.000s	2.795ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	14.000s	2.795ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.890m	4.755ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.780s	5.462us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	26.420s	6.893ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.780s	5.462us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.780s	5.462us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	14.000s	2.795ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.780s	5.462us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	5.710s	557.096us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.48652391944957784014635972684335783128246219978702377917435833583218831566150
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @ 660284186 ps: (cip_tl_seq_item.sv:216) [req] d_user.data_intg act (0xc) != exp (0x33)
        UVM_INFO @ 660284186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.87637217338632968414687349050283649931004899813765603326619600476658568364131
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @   5462111 ps: (prim_fifo_sync.sv:218) [ASSERT FAILED] DataKnown_A
        UVM_INFO @   5462111 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---