SRAM_CTRL/RET Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	7.740s	1.742ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.690s	20.451us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.630s	23.192us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.890s	308.202us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.790s	26.114us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.910s	36.790us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.630s	23.192us	1	1	100.00
		sram_ctrl_csr_aliasing	1.790s	26.114us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	9.010s	1.314ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.800s	159.519us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	1.373m	5.659ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.952m	13.201ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	47.570s	3.852ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.069m	30.906ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	6.650s	601.121us	1	1	100.00
V2	executable	sram_ctrl_executable	7.563m	22.476ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	12.520s	977.922us	1	1	100.00
		sram_ctrl_partial_access_b2b	4.087m	49.289ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	18.570s	99.858us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	46.550s	152.852us	1	1	100.00
		sram_ctrl_throughput_w_readback	38.300s	260.945us	1	1	100.00
V2	regwen	sram_ctrl_regwen	13.444m	15.178ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.890s	90.639us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	34.106m	243.578ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.590s	14.867us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.210s	44.168us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.210s	44.168us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.690s	20.451us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	23.192us	1	1	100.00
		sram_ctrl_csr_aliasing	1.790s	26.114us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.790s	66.941us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.690s	20.451us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	23.192us	1	1	100.00
		sram_ctrl_csr_aliasing	1.790s	26.114us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.790s	66.941us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.440s	218.464us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.590s	8.138us	0	1	0.00
		sram_ctrl_tl_intg_err	3.990s	1.876ms	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.590s	8.138us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.990s	1.876ms	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	13.444m	15.178ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	13.444m	15.178ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.630s	23.192us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	7.563m	22.476ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	7.563m	22.476ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	7.563m	22.476ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	6.650s	601.121us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.900s	120.113us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.440s	218.464us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.790s	55.590us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	7.740s	1.742ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	7.740s	1.742ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	7.563m	22.476ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.590s	8.138us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	6.650s	601.121us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.590s	8.138us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.590s	8.138us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	7.740s	1.742ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.590s	8.138us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	57.920s	515.812us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.44482888227374539170716531947841045727897347473496356400424166737311560508074
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   8138380 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   8138380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---