UART Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: 63d024d

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	13.740s	5.867ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.370s	44.355us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.590s	12.119us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.040s	35.458us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.850s	66.591us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.760s	52.726us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.590s	12.119us	1	1	100.00
		uart_csr_aliasing	1.850s	66.591us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	30.510s	29.884ms	1	1	100.00
V2	parity	uart_smoke	13.740s	5.867ms	1	1	100.00
		uart_tx_rx	30.510s	29.884ms	1	1	100.00
V2	parity_error	uart_intr	1.894m	201.051ms	1	1	100.00
		uart_rx_parity_err	44.650s	36.323ms	1	1	100.00
V2	watermark	uart_tx_rx	30.510s	29.884ms	1	1	100.00
		uart_intr	1.894m	201.051ms	1	1	100.00
V2	fifo_full	uart_fifo_full	25.440s	70.823ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	38.820s	138.905ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.346m	118.994ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.894m	201.051ms	1	1	100.00
V2	rx_break_err	uart_intr	1.894m	201.051ms	1	1	100.00
V2	rx_timeout	uart_intr	1.894m	201.051ms	1	1	100.00
V2	perf	uart_perf	1.484m	11.594ms	1	1	100.00
V2	sys_loopback	uart_loopback	3.080s	3.366ms	1	1	100.00
V2	line_loopback	uart_loopback	3.080s	3.366ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	18.730s	48.586ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.970s	5.436ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.790s	1.098ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	42.330s	7.174ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.770m	31.743ms	1	1	100.00
V2	stress_all	uart_stress_all	2.092m	1.694s	1	1	100.00
V2	alert_test	uart_alert_test	1.600s	21.412us	1	1	100.00
V2	intr_test	uart_intr_test	1.520s	63.922us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.710s	148.836us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.710s	148.836us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.370s	44.355us	1	1	100.00
		uart_csr_rw	1.590s	12.119us	1	1	100.00
		uart_csr_aliasing	1.850s	66.591us	1	1	100.00
		uart_same_csr_outstanding	1.780s	20.428us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.370s	44.355us	1	1	100.00
		uart_csr_rw	1.590s	12.119us	1	1	100.00
		uart_csr_aliasing	1.850s	66.591us	1	1	100.00
		uart_same_csr_outstanding	1.780s	20.428us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.800s	626.639us	1	1	100.00
		uart_tl_intg_err	2.280s	578.406us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.280s	578.406us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	8.750s	714.593us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00