CHIP Simulation Results

Tuesday May 13 2025 17:00:54 UTC

GitHub Revision: `63d024d`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	1.980m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	1.980m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.273m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.107m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	43.825s		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.231m	5.904ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.231m	5.904ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.231m	5.904ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	39.190s	10.360us	0	1	0.00
		chip_sw_example_manufacturer	2.632m		0	1	0.00
		chip_sw_example_concurrency	3.611m	4.866ms	1	1	100.00
		chip_sw_uart_smoketest_signed	15.143s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	10.660s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	12.060s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	12.060s		0	1	0.00
V1	xbar_smoke	xbar_smoke	21.880s	58.912us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	1.827m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	9.747m	9.407ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.329m	4.493ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	19.295s		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	18.530s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	38.309s		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	29.170s		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.000s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.000s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.561m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.229m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.387m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.387m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.927m	4.864ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	3.499m	4.407ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.862m	14.945ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.393s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.167s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	4.140m	8.672ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.887m	5.202ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	23.013m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	23.013m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	20.918s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.149m	4.307ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.149m	4.307ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.958m	18.017ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.584m	5.129ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.664m	4.902ms	1	1	100.00
		chip_sw_aes_idle	4.652m	4.698ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.725m	5.643ms	1	1	100.00
		chip_sw_kmac_idle	3.640m	5.181ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.137m	12.017ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	13.214m	12.016ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	13.191m	12.015ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.962m	12.014ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	15.398s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.501s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.704s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.443s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.578s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	15.321s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.243s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.398s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.501s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.704s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.443s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.578s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	15.321s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.243s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.710s		0	1	0.00
		chip_sw_aes_enc_jitter_en	59.420s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	50.190s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.080s	10.260us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	50.310s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.974s		0	1	0.00
		chip_sw_clkmgr_jitter	4.232m	4.214ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.381m	5.473ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.141s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	49.660s	10.220us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	47.720s	10.400us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	50.340s	10.300us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	46.600s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	47.470s	10.220us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.474s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.729s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	15.417s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.606s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	19.385m	16.572ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	11.499m	15.086ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.149m	4.307ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.594s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	11.499m	15.086ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	13.672s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.278s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	11.190s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	14.522s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	10.998s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	19.385m	16.572ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.862m	14.945ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	23.539m	20.021ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	5.949m	7.056ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	9.746m	8.995ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.976m	4.866ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	19.385m	16.572ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	11.895s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.182s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	19.385m	16.572ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.326s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	9.746m	8.995ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.521s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.401s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.948s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.226s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.148s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	11.298s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.182s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	18.218s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.759s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	18.218s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	18.218s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	18.218s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.295m	5.914ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.009s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.097s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.988s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.723s		0	1	0.00
		chip_sw_lc_ctrl_transition	18.218s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	7.562m	9.095ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.625m	14.941ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	10.957s		0	1	0.00
		chip_prim_tl_access	12.738m	15.256ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.398s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.501s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	10.704s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.443s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	18.578s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	15.321s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	12.243s		0	1	0.00
		chip_rv_dm_lc_disabled	4.140m	8.672ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.678m	3.800ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	59.420s	10.320us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.396m	4.621ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.652m	4.698ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.544m	4.158ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	50.190s	10.240us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.725m	5.643ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.082m	5.268ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.601m	4.220ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	50.310s	10.260us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	7.562m	9.095ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	18.218s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	38.690s	10.260us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.875m	5.503ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.640m	5.181ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.677s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.677s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.864s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.690m	5.471ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	14.091s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	7.562m	9.095ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.080s	10.260us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	12.377s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	11.710s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.664m	4.902ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.664m	4.902ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.664m	4.902ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.092m	4.317ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.625m	14.941ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.625m	14.941ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.002m	8.809ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.974s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.957s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	19.385m	16.572ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.387m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	18.218s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.092m	4.317ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.562m	9.095ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.002m	8.809ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.262m	3.921ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.092m	4.317ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	7.562m	9.095ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.002m	8.809ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.262m	3.921ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	18.218s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.068s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	16.759s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.009s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	14.097s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	14.988s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.723s		0	1	0.00
		chip_sw_lc_ctrl_transition	18.218s		0	1	0.00
		chip_prim_tl_access	12.738m	15.256ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	12.738m	15.256ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	26.905s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	1.059m		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.729s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	11.710s		0	1	0.00
		chip_sw_aes_enc_jitter_en	59.420s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	50.190s	10.240us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	48.080s	10.260us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	50.310s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	11.974s		0	1	0.00
		chip_sw_clkmgr_jitter	4.232m	4.214ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.772m	8.896ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.772m	8.896ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.221m	5.478ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.028m	4.401ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.458m	5.039ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.992m	5.067ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.982m	3.827ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.418m	4.735ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.262m	3.921ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	23.539m	20.021ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	23.539m	20.021ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.357m	3.295ms	1	1	100.00
		chip_sw_aon_timer_smoketest	4.091m	4.727ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.060m	4.752ms	1	1	100.00
		chip_sw_csrng_smoketest	3.567m	3.751ms	1	1	100.00
		chip_sw_gpio_smoketest	3.557m	3.624ms	1	1	100.00
		chip_sw_hmac_smoketest	4.105m	4.095ms	1	1	100.00
		chip_sw_kmac_smoketest	3.772m	4.081ms	1	1	100.00
		chip_sw_otbn_smoketest	4.730m	3.782ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.708m	3.362ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.589m	4.062ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.227m	5.968ms	1	1	100.00
		chip_sw_rstmgr_smoketest	4.036m	5.193ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.805m	4.629ms	1	1	100.00
		chip_sw_uart_smoketest	3.520m	4.800ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	14.939s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	15.143s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	1.827m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	13.113s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.082m	5.889ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.884m	4.706ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.601m	4.549ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.240m	4.053ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	14.121s		0	1	0.00
		chip_rv_dm_lc_disabled	4.140m	8.672ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	55.765s		0	1	0.00
		chip_sw_lc_walkthrough_prod	31.117s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	17.085s		0	1	0.00
		chip_sw_lc_walkthrough_rma	11.819s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	14.121s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	16.984s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	21.082s		0	1	0.00
		rom_volatile_raw_unlock	10.762s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.657s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.465m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	1.448m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	3.199m	3.888ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	3.199m	3.888ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	12.060s		0	1	0.00
		chip_same_csr_outstanding	10.990s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	12.060s		0	1	0.00
		chip_same_csr_outstanding	10.990s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	2.638m	426.174us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	11.870s	12.670us	1	1	100.00
		xbar_smoke_large_delays	4.973m	2.659ms	1	1	100.00
		xbar_smoke_slow_rsp	5.045m	1.877ms	1	1	100.00
		xbar_random_zero_delays	18.350s	18.918us	1	1	100.00
		xbar_random_large_delays	4.986m	2.657ms	1	1	100.00
		xbar_random_slow_rsp	15.799m	5.720ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.248m	142.677us	1	1	100.00
		xbar_error_and_unmapped_addr	1.433m	170.399us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	1.730m	326.312us	1	1	100.00
		xbar_error_and_unmapped_addr	1.433m	170.399us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.130m	655.822us	1	1	100.00
		xbar_access_same_device_slow_rsp	27.828m	10.626ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	22.090s	62.095us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	5.577m	954.991us	1	1	100.00
		xbar_stress_all_with_error	2.708m	462.493us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	6.316m	308.214us	1	1	100.00
		xbar_stress_all_with_reset_error	12.518m	643.218us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	13.215s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.632s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	14.031s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.870s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.258s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.242s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	11.343s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	11.405s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.690s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	10.864s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.421s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.057s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.291s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	12.103s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.334s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.584s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	13.515s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	13.019s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.950s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.664s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.414s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.731s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.627s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.512s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.489s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	11.549s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.980s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.042s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.172s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.278s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.199s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.626s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.297s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.642s		0	1	0.00
		rom_e2e_asm_init_dev	11.741s		0	1	0.00
		rom_e2e_asm_init_prod	11.604s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.476s		0	1	0.00
		rom_e2e_asm_init_rma	11.040s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.940s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.503s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.107s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.890s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.578m	4.649ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.424m	4.723ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.573s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.319s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.935s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.944s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	19.385m	16.572ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	15.696s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	16.980m	12.999ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.050s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.177s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.573s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.319s		0	1	0.00
		rom_e2e_jtag_debug_rma	11.935s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	11.104s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.369s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.367s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.156m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	20.336m	14.255ms	1	1	100.00
		chip_plic_all_irqs_0	9.000m	6.215ms	1	1	100.00
		chip_plic_all_irqs_10	10.174m	6.887ms	1	1	100.00
		chip_sw_dma_inline_hashing	3.980m	5.592ms	1	1	100.00
		chip_sw_dma_abort	4.580m	5.663ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.804s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.301s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.005s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.326s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.547s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.454s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	11.066s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	10.812s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.915s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.481s		0	1	0.00
		chip_sw_mbx_smoketest	4.291m	6.298ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.60888944507904822779202914148208986017448571202223086993457082280234012958312
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (dd75de)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 137.331s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.14968110234169726009344697940106167286547588121891358598837260828809249726328
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (55780e)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 132.741s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.32334930565169699503353497111081034960800199642123391557019469276680169249526
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (f33418)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 142.273s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.79978352376660127724492092587249462086404620448883216500594193802049394504688
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Target //sw/device/tests:sleep_pin_retention_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (7de129)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 123.074s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.4832337351365314284869389812239743122357875183210615619539744549100746988854
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (625ead)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 107.055s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.87713911346505730959681379607568650022326063739747389179777554372044519518836
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.105181573996650291780734419894851803618762317024644925724864175622268859936930
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.14208432594747709413079681644275157743000257738940282614327743682612282005085
    Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.58063336851151815653886412221223646482344338821220776168835866433007828873382
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.88148907829648393849843996897121710122681189209718335702762009901139605799957
    Line 416, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.9199725705611350630769342474397941415278779159226720721171564598893820315589
Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12016.886387 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.886387 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.95504077939531364237300046470851509773951714167996750055349780883371645931435
Line 441, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12016.107326 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.107326 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.108492333445302907508292398675932050774718553911147580685370362997608078558623
Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12015.339245 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12015.339245 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.85028301464562806421975167303417600818916081056592145419100481037559202588048
Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12014.389013 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.389013 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.73098486495894541409931077792107209539995205511310503662384837918270325498542
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.103450547043080052275240396000293903205523722698709217692671971157907402858112
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.24282037050422532171226922171386742376911878432257747240269952175232126940397
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.91480879414480368277818897249956619371919435161872243065939522956516908456803
Line 461, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20021.404819 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20021.404819 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.38042947792247254196665983926893699702371118400161402513506591471388207173197
Line 449, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18017.262261 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18017.262261 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.15585812738339126424425926640900782339714098656585659021068358563430209509815
Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18016.831961 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.831961 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.108781672048089066196755853384470720399675691394624832662041185469082717400312
Line 489, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9094.578150 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (58409579736992102138590280409708810777070567553108803033908417021601672533685 [0x8122a68c31f7a1e26f110390d057071016a87f499f1bb1231ed264c37bab16b5] vs 33845499828482612315968670348719090289501504924468825773682908845267144996564 [0x4ad3dfc15e7552c46b0da230d78de8d872f3834f90d6c970575a962caa80f6d4])
  UVM_INFO @ 9094.578150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.97637951356776711696816663419956252464195476358001910018178605263728488530427
Line 486, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 5913.788216 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (25071728266813125844981441716490946838372616658060672206864147515582905336534 [0x376e1866f4ce1083067ec4a3aa37775454aeb767e618c33737082ca7b42842d6] vs 20029365513021130615732739124545234474844383667871109083294978096479822570947 [0x2c4838198d7a2406906d24bdb07f1c5617d70d3c315607372d704e7c039a65c3])
  UVM_INFO @ 5913.788216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.92166567058109350177645470965936628521459036571067485393521243738788862602968
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4864.141964 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h3f091aaa  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h19  a_opcode: 'h1  a_user: 'h248d0  d_param: 'h0  d_source: 'h19  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4864.141964 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.72834091336171220097287984581744923790365211245799657839624042871486664723069
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 4406.996344 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h85828fdf  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h39  a_opcode: 'h0  a_user: 'h26914  d_param: 'h0  d_source: 'h39  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4406.996344 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.66714648716213025783221767494302973897274709024692395650841596448281806778434
    Line 401, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.33920463938811019292906664983613880260327966749479386921458313061517810003479
    Line 463, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4493.098368 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4493.098368 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.2613888843577558282832306300923766204212025715991516907552938027853625059828
    Line 671, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 8995.292576 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 8995.292576 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.51170865678369347712319100996344879828550025026160249003061746307120784751846
    Line 454, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5478.235180 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5478.235180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.79202986243813695440623325195335747601819657741387406970078717469322116075312
    Line 450, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4401.082832 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4401.082832 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.80590668173739239564925770626882179171420413999445651176374589131948721855650
    Line 464, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4306.614174 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4306.614174 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.38221238358499885450765662106578901941626612655802449157827654803103753204926
    Line 420, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5067.441296 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5067.441296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.18827516978028501483438404544034245757373018694577013485774144791736617536172
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.260001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@37280) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.60485775646135443886981683503130018789431624167246127997994593281268468427484
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 3888.472680 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@37280) { a_addr: 'h2210  a_data: 'h866aded9  a_mask: 'h1  a_size: 'h1  a_param: 'h0  a_source: 'hc5  a_opcode: 'h4  a_user: 'h26088  d_param: 'h0  d_source: 'hc5  d_data: 'h0  d_size: 'h1  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h12a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3888.472680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.46926010944136176420817624053119416396504748578422000068841251343686950768160
    Line 401, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14944.675740 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14944.675740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.56603056546602683510714142516039200353230465066428959179950118510993081174640
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.91650310894799998158966389648749432059151419547421820210179234231003252657262
    Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5663.025648 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5663.025648 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```