DMA Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	330.045us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	1.594ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	1.189ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	13.401us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	56.557us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	12.000s	297.218us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	8.000s	873.514us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	29.110us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	56.557us	1	1	100.00
		dma_csr_aliasing	8.000s	873.514us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	52.000s	2.827ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	34.067m	385.236ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	2.333m	11.967ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	27.733m	3.456s	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	34.067m	385.236ms	1	1	100.00
V2	dma_abort	dma_abort	7.000s	303.960us	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.317m	25.055ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	30.910us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	129.742us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	129.742us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	13.401us	1	1	100.00
		dma_csr_rw	4.000s	56.557us	1	1	100.00
		dma_csr_aliasing	8.000s	873.514us	1	1	100.00
		dma_same_csr_outstanding	5.000s	297.491us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	13.401us	1	1	100.00
		dma_csr_rw	4.000s	56.557us	1	1	100.00
		dma_csr_aliasing	8.000s	873.514us	1	1	100.00
		dma_same_csr_outstanding	5.000s	297.491us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	19.000s	741.707us	1	1	100.00
		dma_generic_stress	27.733m	3.456s	1	1	100.00
		dma_handshake_stress	34.067m	385.236ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	5.000s	1.155ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.833m	44.617ms	1	1	100.00
		dma_longer_transfer	9.000s	304.513us	1	1	100.00
		TOTAL			21	21	100.00