HMAC Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 7.130s 845.803us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.700s 39.916us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.460s 60.342us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 12.410s 17.570ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.240s 309.925us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.980s 111.956us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.460s 60.342us 1 1 100.00
hmac_csr_aliasing 3.240s 309.925us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 47.710s 7.336ms 1 1 100.00
V2 back_pressure hmac_back_pressure 1.038m 6.566ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.190s 1.067ms 1 1 100.00
hmac_test_sha384_vectors 5.426m 20.532ms 1 1 100.00
hmac_test_sha512_vectors 6.838m 11.701ms 1 1 100.00
hmac_test_hmac256_vectors 7.510s 369.045us 1 1 100.00
hmac_test_hmac384_vectors 11.230s 350.448us 1 1 100.00
hmac_test_hmac512_vectors 8.910s 1.319ms 1 1 100.00
V2 burst_wr hmac_burst_wr 12.080s 3.309ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.540m 1.124ms 1 1 100.00
V2 error hmac_error 7.730s 191.189us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.318m 6.379ms 1 1 100.00
V2 save_and_restore hmac_smoke 7.130s 845.803us 1 1 100.00
hmac_long_msg 47.710s 7.336ms 1 1 100.00
hmac_back_pressure 1.038m 6.566ms 1 1 100.00
hmac_datapath_stress 1.540m 1.124ms 1 1 100.00
hmac_burst_wr 12.080s 3.309ms 1 1 100.00
hmac_stress_all 22.980s 6.811ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 7.130s 845.803us 1 1 100.00
hmac_long_msg 47.710s 7.336ms 1 1 100.00
hmac_back_pressure 1.038m 6.566ms 1 1 100.00
hmac_datapath_stress 1.540m 1.124ms 1 1 100.00
hmac_wipe_secret 1.318m 6.379ms 1 1 100.00
hmac_test_sha256_vectors 9.190s 1.067ms 1 1 100.00
hmac_test_sha384_vectors 5.426m 20.532ms 1 1 100.00
hmac_test_sha512_vectors 6.838m 11.701ms 1 1 100.00
hmac_test_hmac256_vectors 7.510s 369.045us 1 1 100.00
hmac_test_hmac384_vectors 11.230s 350.448us 1 1 100.00
hmac_test_hmac512_vectors 8.910s 1.319ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 7.130s 845.803us 1 1 100.00
hmac_long_msg 47.710s 7.336ms 1 1 100.00
hmac_back_pressure 1.038m 6.566ms 1 1 100.00
hmac_datapath_stress 1.540m 1.124ms 1 1 100.00
hmac_burst_wr 12.080s 3.309ms 1 1 100.00
hmac_error 7.730s 191.189us 1 1 100.00
hmac_wipe_secret 1.318m 6.379ms 1 1 100.00
hmac_test_sha256_vectors 9.190s 1.067ms 1 1 100.00
hmac_test_sha384_vectors 5.426m 20.532ms 1 1 100.00
hmac_test_sha512_vectors 6.838m 11.701ms 1 1 100.00
hmac_test_hmac256_vectors 7.510s 369.045us 1 1 100.00
hmac_test_hmac384_vectors 11.230s 350.448us 1 1 100.00
hmac_test_hmac512_vectors 8.910s 1.319ms 1 1 100.00
hmac_stress_all 22.980s 6.811ms 1 1 100.00
V2 stress_all hmac_stress_all 22.980s 6.811ms 1 1 100.00
V2 alert_test hmac_alert_test 1.440s 23.920us 1 1 100.00
V2 intr_test hmac_intr_test 1.560s 20.473us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.880s 99.371us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.880s 99.371us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.700s 39.916us 1 1 100.00
hmac_csr_rw 1.460s 60.342us 1 1 100.00
hmac_csr_aliasing 3.240s 309.925us 1 1 100.00
hmac_same_csr_outstanding 1.960s 236.873us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.700s 39.916us 1 1 100.00
hmac_csr_rw 1.460s 60.342us 1 1 100.00
hmac_csr_aliasing 3.240s 309.925us 1 1 100.00
hmac_same_csr_outstanding 1.960s 236.873us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.820s 95.133us 1 1 100.00
hmac_tl_intg_err 3.880s 272.370us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.880s 272.370us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 7.130s 845.803us 1 1 100.00
V3 stress_reset hmac_stress_reset 2.530s 120.462us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.897m 13.800ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.900s 8.946us 1 1 100.00
TOTAL 28 28 100.00