I2C Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: `70ecaeb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	21.700s	6.515ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.870s	2.431ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.680s	56.556us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.560s	26.890us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.490s	65.123us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.250s	76.612us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.420s	59.146us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.560s	26.890us	1	1	100.00
		i2c_csr_aliasing	2.250s	76.612us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	7.590s	533.234us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	1.314m	4.761ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	31.880s	27.383ms	1	1	100.00
V2	host_override	i2c_host_override	1.620s	295.641us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.915m	3.086ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	47.130s	2.725ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.790s	137.629us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.510s	754.433us	1	1	100.00
		i2c_host_fifo_reset_rx	4.120s	176.035us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.055m	7.221ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.470s	539.268us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.210s	82.705us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.780s	4.698ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	49.220s	9.554ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	2.860s	1.138ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	14.560s	2.270ms	1	1	100.00
		i2c_target_intr_smoke	7.100s	766.156us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.750s	328.387us	1	1	100.00
		i2c_target_fifo_reset_tx	2.000s	544.359us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	52.490s	42.507ms	1	1	100.00
		i2c_target_stress_rd	14.560s	2.270ms	1	1	100.00
		i2c_target_intr_stress_wr	13.980s	8.754ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.750s	1.279ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	4.780s	2.248ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	4.030s	686.475us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.650s	1.113ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.910s	973.897us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.910s	113.610us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	31.880s	27.383ms	1	1	100.00
		i2c_host_perf_precise	21.060s	737.413us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.470s	539.268us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.410s	344.221us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.920s	2.025ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.890s	509.364us	1	1	100.00
		i2c_target_nack_txstretch	2.240s	1.934ms	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	5.260s	2.244ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.320s	1.739ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.550s	50.659us	1	1	100.00
V2	intr_test	i2c_intr_test	1.510s	54.477us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.630s	164.531us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.630s	164.531us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.680s	56.556us	1	1	100.00
		i2c_csr_rw	1.560s	26.890us	1	1	100.00
		i2c_csr_aliasing	2.250s	76.612us	1	1	100.00
		i2c_same_csr_outstanding	1.550s	34.826us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.680s	56.556us	1	1	100.00
		i2c_csr_rw	1.560s	26.890us	1	1	100.00
		i2c_csr_aliasing	2.250s	76.612us	1	1	100.00
		i2c_same_csr_outstanding	1.550s	34.826us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.400s	254.268us	1	1	100.00
		i2c_sec_cm	1.870s	274.785us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.400s	254.268us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	14.870s	1.045ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.730s	44.853us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	11.210s	1.746ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.109823381292930948047112971416646428021816859422109704593061385829664821518801
Line 188, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 4760728807 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @1233152

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.105265595238617440144639092838594274867715194926241862762285177000303124372600
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @  82704890 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @10007

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.85695634423093784798628236954522179428669433401255000223620782140112603492134
    Line 127, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1045191516 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1045191516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.64433591588307797039784242477360434876706075643177043715625051177083713375232
    Line 91, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1746087198 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1746087198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.61918009960676925973511696993660483041574849850378934580466318071247178528794
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @  44852908 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 252 [0xfc])
  UVM_INFO @  44852908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```