KEYMGR Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	3.550s	130.208us	1	1	100.00
V1	random	keymgr_random	3.850s	76.669us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.840s	285.162us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	2.190s	25.428us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	10.190s	451.386us	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	4.890s	369.179us	0	1	0.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.320s	34.332us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	2.190s	25.428us	1	1	100.00
		keymgr_csr_aliasing	4.890s	369.179us	0	1	0.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	5.600s	465.836us	1	1	100.00
V2	sideload	keymgr_sideload	3.980s	295.970us	1	1	100.00
		keymgr_sideload_kmac	4.760s	300.268us	1	1	100.00
		keymgr_sideload_aes	3.020s	163.821us	1	1	100.00
		keymgr_sideload_otbn	7.070s	747.299us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	2.640s	200.876us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	5.070s	122.915us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.340s	97.948us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	3.830s	133.278us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	2.590s	113.418us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.930s	108.859us	1	1	100.00
V2	stress_all	keymgr_stress_all	29.530s	4.635ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.530s	12.170us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.630s	20.354us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	2.600s	385.750us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	2.600s	385.750us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.840s	285.162us	1	1	100.00
		keymgr_csr_rw	2.190s	25.428us	1	1	100.00
		keymgr_csr_aliasing	4.890s	369.179us	0	1	0.00
		keymgr_same_csr_outstanding	2.650s	195.675us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.840s	285.162us	1	1	100.00
		keymgr_csr_rw	2.190s	25.428us	1	1	100.00
		keymgr_csr_aliasing	4.890s	369.179us	0	1	0.00
		keymgr_same_csr_outstanding	2.650s	195.675us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	6.250s	438.210us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	6.250s	438.210us	1	1	100.00
		keymgr_tl_intg_err	3.590s	355.904us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	5.460s	283.529us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	5.460s	283.529us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	5.460s	283.529us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	5.460s	283.529us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	5.480s	149.445us	1	1	100.00
V2S	prim_count_check	keymgr_sec_cm	6.250s	438.210us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	6.250s	438.210us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	3.590s	355.904us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	5.460s	283.529us	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	5.600s	465.836us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	3.850s	76.669us	1	1	100.00
		keymgr_csr_rw	2.190s	25.428us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	3.850s	76.669us	1	1	100.00
		keymgr_csr_rw	2.190s	25.428us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	3.850s	76.669us	1	1	100.00
		keymgr_csr_rw	2.190s	25.428us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	5.070s	122.915us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	2.590s	113.418us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	2.590s	113.418us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	3.850s	76.669us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	3.410s	453.748us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	6.250s	438.210us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	6.250s	438.210us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	6.250s	438.210us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	4.190s	181.890us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	5.070s	122.915us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	6.250s	438.210us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	6.250s	438.210us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	6.250s	438.210us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	4.190s	181.890us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	4.190s	181.890us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	6.250s	438.210us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	4.190s	181.890us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	6.250s	438.210us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	4.190s	181.890us	1	1	100.00
V2S		TOTAL			6	6	100.00
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	7.640s	237.694us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	30	96.67

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test keymgr_csr_aliasing has 1 failures.

    • 0.keymgr_csr_aliasing.97887688396839874398758926504185406806212184831817065771234830496842809283847
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[16] & 'hffffffff)))'
        UVM_ERROR @ 369179085 ps: (keymgr_csr_assert_fpv.sv:449) [ASSERT FAILED] attest_sw_binding_3_rd_A
        UVM_INFO @ 369179085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---