KMAC/MASKED Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	15.660s	503.240us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.020s	52.614us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.900s	17.329us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.310s	677.827us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	7.420s	4.369ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.530s	78.509us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.900s	17.329us	1	1	100.00
		kmac_csr_aliasing	7.420s	4.369ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.740s	27.256us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.070s	105.728us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	13.922m	150.873ms	1	1	100.00
V2	burst_write	kmac_burst_write	6.707m	20.544ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	35.530s	11.193ms	1	1	100.00
		kmac_test_vectors_sha3_256	33.770s	9.020ms	1	1	100.00
		kmac_test_vectors_sha3_384	25.187m	165.935ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.040s	1.067ms	1	1	100.00
		kmac_test_vectors_shake_128	2.917m	46.900ms	1	1	100.00
		kmac_test_vectors_shake_256	5.016m	21.539ms	1	1	100.00
		kmac_test_vectors_kmac	2.840s	93.877us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.570s	69.080us	1	1	100.00
V2	sideload	kmac_sideload	4.139m	40.638ms	1	1	100.00
V2	app	kmac_app	1.228m	11.910ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.140m	10.679ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.462m	65.455ms	1	1	100.00
V2	error	kmac_error	1.056m	2.421ms	1	1	100.00
V2	key_error	kmac_key_error	4.800s	451.003us	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	6.090s	400.515us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.770s	45.460us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.070s	17.537us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	17.140s	11.410ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.360s	47.466us	1	1	100.00
V2	stress_all	kmac_stress_all	5.228m	11.293ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.820s	15.151us	1	1	100.00
V2	alert_test	kmac_alert_test	1.690s	54.989us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	4.110s	372.633us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	4.110s	372.633us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.020s	52.614us	1	1	100.00
		kmac_csr_rw	1.900s	17.329us	1	1	100.00
		kmac_csr_aliasing	7.420s	4.369ms	1	1	100.00
		kmac_same_csr_outstanding	2.650s	150.955us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.020s	52.614us	1	1	100.00
		kmac_csr_rw	1.900s	17.329us	1	1	100.00
		kmac_csr_aliasing	7.420s	4.369ms	1	1	100.00
		kmac_same_csr_outstanding	2.650s	150.955us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.640s	60.637us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.640s	60.637us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.640s	60.637us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.640s	60.637us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.270s	201.278us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	1.157m	8.398ms	1	1	100.00
		kmac_tl_intg_err	1.670s	38.770us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.670s	38.770us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.360s	47.466us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	15.660s	503.240us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.139m	40.638ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.640s	60.637us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.157m	8.398ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.157m	8.398ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.157m	8.398ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	15.660s	503.240us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.360s	47.466us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.157m	8.398ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	4.186m	43.732ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	15.660s	503.240us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	39.640s	1.201ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.89136080921200803394840500006846981990102832327635718342705163826627977456090
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
        UVM_ERROR @  38770160 ps: (kmac_csr_assert_fpv.sv:505) [ASSERT FAILED] prefix_2_rd_A
        UVM_INFO @  38770160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---