KMAC/UNMASKED Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	28.280s	1.900ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.980s	137.468us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.890s	20.151us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	11.110s	708.311us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	6.920s	1.596ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.960s	127.566us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.890s	20.151us	1	1	100.00
		kmac_csr_aliasing	6.920s	1.596ms	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.680s	12.183us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.840s	30.160us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	10.608m	39.617ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.824m	19.845ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.940m	135.800ms	1	1	100.00
		kmac_test_vectors_sha3_256	23.038m	143.775ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.880s	5.279ms	1	1	100.00
		kmac_test_vectors_sha3_512	9.050m	18.485ms	1	1	100.00
		kmac_test_vectors_shake_128	2.487m	28.581ms	1	1	100.00
		kmac_test_vectors_shake_256	16.402m	17.078ms	1	1	100.00
		kmac_test_vectors_kmac	2.810s	167.889us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.790s	63.372us	1	1	100.00
V2	sideload	kmac_sideload	4.002m	12.305ms	1	1	100.00
V2	app	kmac_app	3.750s	198.763us	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.121m	29.404ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.817m	5.723ms	1	1	100.00
V2	error	kmac_error	37.060s	2.085ms	1	1	100.00
V2	key_error	kmac_key_error	5.020s	1.034ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	2.860s	40.718us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	10.420s	623.563us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	13.850s	551.691us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	21.460s	2.586ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.400s	41.692us	1	1	100.00
V2	stress_all	kmac_stress_all	9.969m	381.701ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.740s	12.264us	1	1	100.00
V2	alert_test	kmac_alert_test	1.790s	66.583us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.900s	570.485us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.900s	570.485us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.980s	137.468us	1	1	100.00
		kmac_csr_rw	1.890s	20.151us	1	1	100.00
		kmac_csr_aliasing	6.920s	1.596ms	1	1	100.00
		kmac_same_csr_outstanding	2.180s	174.428us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.980s	137.468us	1	1	100.00
		kmac_csr_rw	1.890s	20.151us	1	1	100.00
		kmac_csr_aliasing	6.920s	1.596ms	1	1	100.00
		kmac_same_csr_outstanding	2.180s	174.428us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.390s	419.842us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.390s	419.842us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.390s	419.842us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.390s	419.842us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.080s	79.260us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	38.400s	13.136ms	1	1	100.00
		kmac_tl_intg_err	3.700s	138.407us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	3.700s	138.407us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.400s	41.692us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	28.280s	1.900ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	4.002m	12.305ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.390s	419.842us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	38.400s	13.136ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	38.400s	13.136ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	38.400s	13.136ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	28.280s	1.900ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.400s	41.692us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	38.400s	13.136ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	1.153m	18.959ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	28.280s	1.900ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	51.500s	3.363ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.38982063637233780475722710228443455816611898862949319552234303865501728117447
      Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[41] & 'hffffffff)))'
        UVM_ERROR @  79260343 ps: (kmac_csr_assert_fpv.sv:505) [ASSERT FAILED] prefix_2_rd_A
        UVM_INFO @  79260343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---