70ecaeb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 1.550m | 7.222ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 6.000s | 126.615us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 32.058us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 23.870us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 12.451us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 2.157us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 32.058us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 12.451us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 1.850m | 9.149ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 13.000s | 480.983us | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 11.000s | 2.984ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 4.000s | 12.623us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 13.000s | 4.215us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 13.000s | 4.215us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 6.000s | 126.615us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 32.058us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 12.451us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 201.237us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 6.000s | 126.615us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 32.058us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 12.451us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 201.237us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 4.000s | 21.924us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 10.000s | 30.281us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_errors has 1 failures.
0.mbx_tl_errors.86565053691897185638860180714969932594838293933105483941896519613043652857044
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 4214723 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x6c53b158 a_data = 0xdda4bb5d a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x4e a_opcode = PutPartialData a_user = 0x1b23b d_data = 0xe2b97899 d_size = 0x3 d_param = 0x0 d_source = 0x97 d_opcode = AccessAck d_error = 0 d_user = 110001100111 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 4214723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_tl_intg_err has 1 failures.
0.mbx_tl_intg_err.88304937174886703559828470810450089203563724063207548866845118868709242863677
Line 95, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 30281212 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x62336908 a_data = 0xd6e1dafd a_mask = 0xe a_size = 0x2 a_param = 0x0 a_source = 0x54 a_opcode = PutPartialData a_user = 0x27367 d_data = 0x427b378e d_size = 0x2 d_param = 0x0 d_source = 0x86 d_opcode = AccessAck d_error = 0 d_user = 10011100001011 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 30281212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_csr_mem_rw_with_rand_reset.105326940219305159101030196750335287141317234043703764920085336547879710489114
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 2157089 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xd78efb4 a_data = 0x6e976011 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0x3b a_opcode = Get a_user = 0x6f5b d_data = 0xe6449b0f d_size = 0x0 d_param = 0x0 d_source = 0xa8 d_opcode = AccessAckData d_error = 0 d_user = 10010000011101 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 2157089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---