ROM_CTRL/32KB Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 5.050s 220.832us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 6.030s 572.486us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 4.360s 538.501us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.030s 4.124ms 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.380s 205.788us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.770s 610.607us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 4.360s 538.501us 1 1 100.00
rom_ctrl_csr_aliasing 5.380s 205.788us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 3.920s 384.879us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 5.670s 1.076ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 4.580s 1.334ms 1 1 100.00
V2 stress_all rom_ctrl_stress_all 14.150s 435.300us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 6.840s 807.078us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 3.890s 385.139us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.790s 146.934us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.790s 146.934us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 6.030s 572.486us 1 1 100.00
rom_ctrl_csr_rw 4.360s 538.501us 1 1 100.00
rom_ctrl_csr_aliasing 5.380s 205.788us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.940s 212.857us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 6.030s 572.486us 1 1 100.00
rom_ctrl_csr_rw 4.360s 538.501us 1 1 100.00
rom_ctrl_csr_aliasing 5.380s 205.788us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.940s 212.857us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.003m 6.480ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 17.900s 1.163ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.547m 1.234ms 1 1 100.00
rom_ctrl_tl_intg_err 21.290s 675.166us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.547m 1.234ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.547m 1.234ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.003m 6.480ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.003m 6.480ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.003m 6.480ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.003m 6.480ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.003m 6.480ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.547m 1.234ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.547m 1.234ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 5.050s 220.832us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 5.050s 220.832us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 5.050s 220.832us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 21.290s 675.166us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.003m 6.480ms 1 1 100.00
rom_ctrl_kmac_err_chk 6.840s 807.078us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.003m 6.480ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.003m 6.480ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.003m 6.480ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 17.900s 1.163ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.547m 1.234ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.920m 1.524ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00