ROM_CTRL/64KB Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 9.240s 308.088us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 8.370s 711.079us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 9.060s 2.773ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.490s 214.122us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.680s 371.346us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 7.320s 1.106ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 9.060s 2.773ms 1 1 100.00
rom_ctrl_csr_aliasing 5.680s 371.346us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.610s 3.576ms 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 8.010s 1.407ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 7.260s 736.390us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 21.770s 849.890us 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 15.270s 566.446us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.230s 498.427us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 11.790s 386.203us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 11.790s 386.203us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 8.370s 711.079us 1 1 100.00
rom_ctrl_csr_rw 9.060s 2.773ms 1 1 100.00
rom_ctrl_csr_aliasing 5.680s 371.346us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.910s 344.959us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 8.370s 711.079us 1 1 100.00
rom_ctrl_csr_rw 9.060s 2.773ms 1 1 100.00
rom_ctrl_csr_aliasing 5.680s 371.346us 1 1 100.00
rom_ctrl_same_csr_outstanding 5.910s 344.959us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 2.330m 7.446ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 36.310s 7.621ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 4.960m 2.674ms 1 1 100.00
rom_ctrl_tl_intg_err 1.099m 3.105ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 4.960m 2.674ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 4.960m 2.674ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.330m 7.446ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.330m 7.446ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.330m 7.446ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 2.330m 7.446ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 2.330m 7.446ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 4.960m 2.674ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 4.960m 2.674ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 9.240s 308.088us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 9.240s 308.088us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 9.240s 308.088us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.099m 3.105ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 2.330m 7.446ms 1 1 100.00
rom_ctrl_kmac_err_chk 15.270s 566.446us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 2.330m 7.446ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 2.330m 7.446ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 2.330m 7.446ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 36.310s 7.621ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 4.960m 2.674ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 40.640s 3.108ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00