RV_TIMER Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.760s	43.392us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.420s	17.220us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.420s	16.336us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.720s	1.245ms	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.590s	36.419us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.490s	39.793us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.420s	16.336us	1	1	100.00
		rv_timer_csr_aliasing	1.590s	36.419us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.880s	359.987us	1	1	100.00
V2	disabled	rv_timer_disabled	2.400s	3.273ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	5.458m	851.750ms	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	5.458m	851.750ms	1	1	100.00
V2	stress	rv_timer_stress_all	2.010s	2.068ms	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.410s	40.089us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.970s	15.333us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.920s	173.043us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.920s	173.043us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.420s	17.220us	1	1	100.00
		rv_timer_csr_rw	1.420s	16.336us	1	1	100.00
		rv_timer_csr_aliasing	1.590s	36.419us	1	1	100.00
		rv_timer_same_csr_outstanding	1.620s	39.686us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.420s	17.220us	1	1	100.00
		rv_timer_csr_rw	1.420s	16.336us	1	1	100.00
		rv_timer_csr_aliasing	1.590s	36.419us	1	1	100.00
		rv_timer_same_csr_outstanding	1.620s	39.686us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.820s	85.239us	1	1	100.00
		rv_timer_tl_intg_err	2.020s	187.831us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.020s	187.831us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	16.450s	2.972ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.560s	43.014us	1	1	100.00
		rv_timer_max	1.420s	60.413us	1	1	100.00
		TOTAL			19	19	100.00