SPI_DEVICE/1R1W Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	46.780s	9.305ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.960s	22.691us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.390s	67.249us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	23.840s	526.078us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	7.680s	7.720ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.640s	595.614us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.390s	67.249us	1	1	100.00
		spi_device_csr_aliasing	7.680s	7.720ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.510s	61.115us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.520s	31.999us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.800s	31.766us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.680s	5.355us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.670s	3.256us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.240s	122.926us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.240s	122.926us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	3.060s	1.680ms	1	1	100.00
		spi_device_tpm_sts_read	1.740s	73.290us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.780s	40.197us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	13.980s	6.472ms	1	1	100.00
		spi_device_flash_all	57.100s	13.143ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.950s	10.529ms	1	1	100.00
		spi_device_flash_all	57.100s	13.143ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.950s	10.529ms	1	1	100.00
		spi_device_flash_all	57.100s	13.143ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	57.100s	13.143ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	9.400s	1.163ms	1	1	100.00
		spi_device_flash_all	57.100s	13.143ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	9.400s	1.163ms	1	1	100.00
		spi_device_flash_all	57.100s	13.143ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	9.400s	1.163ms	1	1	100.00
		spi_device_flash_all	57.100s	13.143ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	9.400s	1.163ms	1	1	100.00
		spi_device_flash_all	57.100s	13.143ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	9.400s	1.163ms	1	1	100.00
		spi_device_flash_all	57.100s	13.143ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	12.960s	23.512ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	6.430s	1.467ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	6.430s	1.467ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	6.430s	1.467ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	14.010s	2.123ms	1	1	100.00
		spi_device_read_buffer_direct	5.580s	2.083ms	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	6.430s	1.467ms	1	1	100.00
		spi_device_flash_all	57.100s	13.143ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	57.100s	13.143ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	57.100s	13.143ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	2.970s	112.519us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	2.970s	112.519us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	46.780s	9.305ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	20.250s	4.586ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.253m	22.257ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.810s	34.388us	1	1	100.00
V2	intr_test	spi_device_intr_test	2.010s	42.918us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.880s	426.407us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.880s	426.407us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.960s	22.691us	1	1	100.00
		spi_device_csr_rw	2.390s	67.249us	1	1	100.00
		spi_device_csr_aliasing	7.680s	7.720ms	1	1	100.00
		spi_device_same_csr_outstanding	2.490s	226.822us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.960s	22.691us	1	1	100.00
		spi_device_csr_rw	2.390s	67.249us	1	1	100.00
		spi_device_csr_aliasing	7.680s	7.720ms	1	1	100.00
		spi_device_same_csr_outstanding	2.490s	226.822us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	1.920s	104.277us	1	1	100.00
		spi_device_tl_intg_err	12.970s	2.359ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	12.970s	2.359ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	55.800s	52.711ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.69478104970919809661184946192601932795353050347717623878997705780201037389059
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   4604861 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[34])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   4604861 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   4604861 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[930])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.45087225432546236511449419185341317052136843909749722255025679372070421414558
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1160308 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc02e4f [110000000010111001001111] vs 0x0 [0])
        UVM_ERROR @   1202308 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1d9f2e [111011001111100101110] vs 0x0 [0])
        UVM_ERROR @   1209308 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xea5340 [111010100101001101000000] vs 0x0 [0])
        UVM_ERROR @   1214308 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3a0405 [1110100000010000000101] vs 0x0 [0])
        UVM_ERROR @   1274308 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x85215b [100001010010000101011011] vs 0x0 [0])