70ecaeb| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | spi_host_smoke | 43.000s | 731.247us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | spi_host_csr_hw_reset | 4.000s | 17.300us | 1 | 1 | 100.00 |
| V1 | csr_rw | spi_host_csr_rw | 4.000s | 38.821us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | spi_host_csr_bit_bash | 6.000s | 253.262us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | spi_host_csr_aliasing | 4.000s | 101.007us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | spi_host_csr_mem_rw_with_rand_reset | 4.000s | 49.732us | 1 | 1 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | spi_host_csr_rw | 4.000s | 38.821us | 1 | 1 | 100.00 |
| spi_host_csr_aliasing | 4.000s | 101.007us | 1 | 1 | 100.00 | ||
| V1 | mem_walk | spi_host_mem_walk | 4.000s | 17.699us | 1 | 1 | 100.00 |
| V1 | mem_partial_access | spi_host_mem_partial_access | 4.000s | 22.331us | 1 | 1 | 100.00 |
| V1 | TOTAL | 8 | 8 | 100.00 | |||
| V2 | performance | spi_host_performance | 4.000s | 23.097us | 1 | 1 | 100.00 |
| V2 | error_event_intr | spi_host_overflow_underflow | 5.000s | 359.290us | 1 | 1 | 100.00 |
| spi_host_error_cmd | 4.000s | 19.130us | 1 | 1 | 100.00 | ||
| spi_host_event | 34.000s | 1.217ms | 1 | 1 | 100.00 | ||
| V2 | clock_rate | spi_host_speed | 6.000s | 487.890us | 1 | 1 | 100.00 |
| V2 | speed | spi_host_speed | 6.000s | 487.890us | 1 | 1 | 100.00 |
| V2 | chip_select_timing | spi_host_speed | 6.000s | 487.890us | 1 | 1 | 100.00 |
| V2 | sw_reset | spi_host_sw_reset | 5.000s | 53.590us | 1 | 1 | 100.00 |
| V2 | passthrough_mode | spi_host_passthrough_mode | 4.000s | 132.205us | 1 | 1 | 100.00 |
| V2 | cpol_cpha | spi_host_speed | 6.000s | 487.890us | 1 | 1 | 100.00 |
| V2 | full_cycle | spi_host_speed | 6.000s | 487.890us | 1 | 1 | 100.00 |
| V2 | duplex | spi_host_smoke | 43.000s | 731.247us | 1 | 1 | 100.00 |
| V2 | tx_rx_only | spi_host_smoke | 43.000s | 731.247us | 1 | 1 | 100.00 |
| V2 | stress_all | spi_host_stress_all | 4.000s | 115.393us | 1 | 1 | 100.00 |
| V2 | spien | spi_host_spien | 5.000s | 1.036ms | 1 | 1 | 100.00 |
| V2 | stall | spi_host_status_stall | 38.000s | 4.421ms | 0 | 1 | 0.00 |
| V2 | Idlecsbactive | spi_host_idlecsbactive | 4.000s | 225.324us | 1 | 1 | 100.00 |
| V2 | data_fifo_status | spi_host_overflow_underflow | 5.000s | 359.290us | 1 | 1 | 100.00 |
| V2 | alert_test | spi_host_alert_test | 4.000s | 130.155us | 1 | 1 | 100.00 |
| V2 | intr_test | spi_host_intr_test | 4.000s | 158.190us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | spi_host_tl_errors | 5.000s | 259.637us | 1 | 1 | 100.00 |
| V2 | tl_d_illegal_access | spi_host_tl_errors | 5.000s | 259.637us | 1 | 1 | 100.00 |
| V2 | tl_d_outstanding_access | spi_host_csr_hw_reset | 4.000s | 17.300us | 1 | 1 | 100.00 |
| spi_host_csr_rw | 4.000s | 38.821us | 1 | 1 | 100.00 | ||
| spi_host_csr_aliasing | 4.000s | 101.007us | 1 | 1 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 22.492us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | spi_host_csr_hw_reset | 4.000s | 17.300us | 1 | 1 | 100.00 |
| spi_host_csr_rw | 4.000s | 38.821us | 1 | 1 | 100.00 | ||
| spi_host_csr_aliasing | 4.000s | 101.007us | 1 | 1 | 100.00 | ||
| spi_host_same_csr_outstanding | 4.000s | 22.492us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 14 | 15 | 93.33 | |||
| V2S | tl_intg_err | spi_host_tl_intg_err | 4.000s | 359.122us | 1 | 1 | 100.00 |
| spi_host_sec_cm | 5.000s | 571.482us | 1 | 1 | 100.00 | ||
| V2S | sec_cm_bus_integrity | spi_host_tl_intg_err | 4.000s | 359.122us | 1 | 1 | 100.00 |
| V2S | TOTAL | 2 | 2 | 100.00 | |||
| Unmapped tests | spi_host_upper_range_clkdiv | 1.100m | 2.675ms | 1 | 1 | 100.00 | |
| TOTAL | 25 | 26 | 96.15 |
xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_*/spi_host_data_stable_sva.sv,104): Assertion NEGEDGE_SAME_VALUE_CHECK_P has failed has 1 failures:
0.spi_host_status_stall.49897997903505460324224839260928131570151874807063401997609387686197939148245
Line 1421, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_status_stall/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/spi_host-sim-xcelium/default/src/lowrisc_dv_spi_host_sva_0.1/spi_host_data_stable_sva.sv,104): (time 4420515966 PS) Assertion tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1].NEGEDGE_SAME_VALUE_CHECK_P has failed
UVM_ERROR @ 4420515966 ps: [NEGEDGE_SAME_VALUE_CHECK_P] tb.dut.spi_host_data_stable_assert.u_sva_cio_sd_i_whole_cycle_data_stable_check.g_signal_stable_sva[1]: [i=1] - ASSERTION FAILED pos_value (0x0) != neg_value (0x0) - time=4420516000 ps
UVM_INFO @ 4420515966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---