SRAM_CTRL/MAIN Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sram_ctrl_smoke 9.230s 795.473us 1 1 100.00
V1 csr_hw_reset sram_ctrl_csr_hw_reset 1.560s 54.158us 1 1 100.00
V1 csr_rw sram_ctrl_csr_rw 1.670s 15.063us 1 1 100.00
V1 csr_bit_bash sram_ctrl_csr_bit_bash 2.470s 55.048us 1 1 100.00
V1 csr_aliasing sram_ctrl_csr_aliasing 1.580s 32.899us 1 1 100.00
V1 csr_mem_rw_with_rand_reset sram_ctrl_csr_mem_rw_with_rand_reset 3.120s 1.377ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr sram_ctrl_csr_rw 1.670s 15.063us 1 1 100.00
sram_ctrl_csr_aliasing 1.580s 32.899us 1 1 100.00
V1 mem_walk sram_ctrl_mem_walk 1.705m 2.744ms 1 1 100.00
V1 mem_partial_access sram_ctrl_mem_partial_access 46.700s 1.945ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 multiple_keys sram_ctrl_multiple_keys 10.621m 24.795ms 1 1 100.00
V2 stress_pipeline sram_ctrl_stress_pipeline 3.183m 15.544ms 1 1 100.00
V2 bijection sram_ctrl_bijection 23.962m 28.446ms 1 1 100.00
V2 access_during_key_req sram_ctrl_access_during_key_req 3.567m 6.554ms 1 1 100.00
V2 lc_escalation sram_ctrl_lc_escalation 1.377m 123.431ms 1 1 100.00
V2 executable sram_ctrl_executable 13.274m 8.320ms 1 1 100.00
V2 partial_access sram_ctrl_partial_access 7.990s 1.800ms 1 1 100.00
sram_ctrl_partial_access_b2b 5.335m 55.515ms 1 1 100.00
V2 max_throughput sram_ctrl_max_throughput 8.690s 725.388us 1 1 100.00
sram_ctrl_throughput_w_partial_write 13.910s 738.998us 1 1 100.00
sram_ctrl_throughput_w_readback 4.780s 2.684ms 1 1 100.00
V2 regwen sram_ctrl_regwen 8.589m 48.792ms 1 1 100.00
V2 ram_cfg sram_ctrl_ram_cfg 4.170s 708.329us 1 1 100.00
V2 stress_all sram_ctrl_stress_all 51.057m 47.310ms 1 1 100.00
V2 alert_test sram_ctrl_alert_test 1.520s 14.039us 1 1 100.00
V2 tl_d_oob_addr_access sram_ctrl_tl_errors 4.220s 428.457us 1 1 100.00
V2 tl_d_illegal_access sram_ctrl_tl_errors 4.220s 428.457us 1 1 100.00
V2 tl_d_outstanding_access sram_ctrl_csr_hw_reset 1.560s 54.158us 1 1 100.00
sram_ctrl_csr_rw 1.670s 15.063us 1 1 100.00
sram_ctrl_csr_aliasing 1.580s 32.899us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.670s 35.333us 1 1 100.00
V2 tl_d_partial_access sram_ctrl_csr_hw_reset 1.560s 54.158us 1 1 100.00
sram_ctrl_csr_rw 1.670s 15.063us 1 1 100.00
sram_ctrl_csr_aliasing 1.580s 32.899us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.670s 35.333us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S passthru_mem_tl_intg_err sram_ctrl_passthru_mem_tl_intg_err 37.560s 58.799ms 1 1 100.00
V2S tl_intg_err sram_ctrl_sec_cm 1.770s 8.337us 0 1 0.00
sram_ctrl_tl_intg_err 2.100s 95.150us 1 1 100.00
V2S prim_count_check sram_ctrl_sec_cm 1.770s 8.337us 0 1 0.00
V2S sec_cm_bus_integrity sram_ctrl_tl_intg_err 2.100s 95.150us 1 1 100.00
V2S sec_cm_ctrl_config_regwen sram_ctrl_regwen 8.589m 48.792ms 1 1 100.00
V2S sec_cm_readback_config_regwen sram_ctrl_regwen 8.589m 48.792ms 1 1 100.00
V2S sec_cm_exec_config_regwen sram_ctrl_csr_rw 1.670s 15.063us 1 1 100.00
V2S sec_cm_exec_config_mubi sram_ctrl_executable 13.274m 8.320ms 1 1 100.00
V2S sec_cm_exec_intersig_mubi sram_ctrl_executable 13.274m 8.320ms 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi sram_ctrl_executable 13.274m 8.320ms 1 1 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi sram_ctrl_lc_escalation 1.377m 123.431ms 1 1 100.00
V2S sec_cm_prim_ram_ctrl_mubi sram_ctrl_mubi_enc_err 5.010s 2.671ms 1 1 100.00
V2S sec_cm_mem_integrity sram_ctrl_passthru_mem_tl_intg_err 37.560s 58.799ms 1 1 100.00
V2S sec_cm_mem_readback sram_ctrl_readback_err 6.900s 3.700ms 1 1 100.00
V2S sec_cm_mem_scramble sram_ctrl_smoke 9.230s 795.473us 1 1 100.00
V2S sec_cm_addr_scramble sram_ctrl_smoke 9.230s 795.473us 1 1 100.00
V2S sec_cm_instr_bus_lc_gated sram_ctrl_executable 13.274m 8.320ms 1 1 100.00
V2S sec_cm_ram_tl_lc_gate_fsm_sparse sram_ctrl_sec_cm 1.770s 8.337us 0 1 0.00
V2S sec_cm_key_global_esc sram_ctrl_lc_escalation 1.377m 123.431ms 1 1 100.00
V2S sec_cm_key_local_esc sram_ctrl_sec_cm 1.770s 8.337us 0 1 0.00
V2S sec_cm_init_ctr_redun sram_ctrl_sec_cm 1.770s 8.337us 0 1 0.00
V2S sec_cm_scramble_key_sideload sram_ctrl_smoke 9.230s 795.473us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun sram_ctrl_sec_cm 1.770s 8.337us 0 1 0.00
V2S TOTAL 4 5 80.00
V3 stress_all_with_rand_reset sram_ctrl_stress_all_with_rand_reset 40.830s 4.832ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 30 31 96.77

Failure Buckets