SRAM_CTRL/RET Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	44.780s	1.823ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.820s	66.314us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.630s	51.139us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.680s	190.343us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.620s	34.125us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.480s	42.393us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.630s	51.139us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	34.125us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.440s	245.119us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	4.030s	57.941us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.287m	1.949ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	1.905m	3.396ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	25.230s	6.047ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	1.652m	1.313ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	8.630s	3.181ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.308m	60.620ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	7.030s	1.472ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.286m	119.948ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	9.380s	287.610us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	57.980s	2.917ms	1	1	100.00
		sram_ctrl_throughput_w_readback	23.660s	188.657us	1	1	100.00
V2	regwen	sram_ctrl_regwen	7.060m	44.497ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.880s	70.264us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	16.349m	7.163ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.560s	25.601us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.160s	164.267us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.160s	164.267us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.820s	66.314us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	51.139us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	34.125us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.640s	14.567us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.820s	66.314us	1	1	100.00
		sram_ctrl_csr_rw	1.630s	51.139us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	34.125us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.640s	14.567us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.670s	1.350ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.510s	5.114us	0	1	0.00
		sram_ctrl_tl_intg_err	3.000s	491.148us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.510s	5.114us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.000s	491.148us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	7.060m	44.497ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	7.060m	44.497ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.630s	51.139us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.308m	60.620ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.308m	60.620ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.308m	60.620ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	8.630s	3.181ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.800s	68.223us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.670s	1.350ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.790s	30.028us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	44.780s	1.823ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	44.780s	1.823ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.308m	60.620ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.510s	5.114us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	8.630s	3.181ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.510s	5.114us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.510s	5.114us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	44.780s	1.823ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.510s	5.114us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	1.220m	11.067ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.99518425668108556348130235894920788177203619025476690420096573509699626467564
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   5114437 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   5114437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---