UART Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: 70ecaeb

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.600s	723.198us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.520s	46.815us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.350s	13.056us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.530s	375.356us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.460s	14.302us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.620s	82.871us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.350s	13.056us	1	1	100.00
		uart_csr_aliasing	1.460s	14.302us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.134m	124.991ms	1	1	100.00
V2	parity	uart_smoke	2.600s	723.198us	1	1	100.00
		uart_tx_rx	1.134m	124.991ms	1	1	100.00
V2	parity_error	uart_intr	29.760s	50.589ms	1	1	100.00
		uart_rx_parity_err	46.020s	195.509ms	1	1	100.00
V2	watermark	uart_tx_rx	1.134m	124.991ms	1	1	100.00
		uart_intr	29.760s	50.589ms	1	1	100.00
V2	fifo_full	uart_fifo_full	52.680s	68.297ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	38.430s	28.674ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	1.691m	91.003ms	1	1	100.00
V2	rx_frame_err	uart_intr	29.760s	50.589ms	1	1	100.00
V2	rx_break_err	uart_intr	29.760s	50.589ms	1	1	100.00
V2	rx_timeout	uart_intr	29.760s	50.589ms	1	1	100.00
V2	perf	uart_perf	3.791m	5.925ms	1	1	100.00
V2	sys_loopback	uart_loopback	12.000s	7.111ms	1	1	100.00
V2	line_loopback	uart_loopback	12.000s	7.111ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	54.650s	106.617ms	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.094m	57.388ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	10.480s	6.507ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	11.220s	2.420ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	1.762m	47.750ms	1	1	100.00
V2	stress_all	uart_stress_all	9.861m	122.486ms	1	1	100.00
V2	alert_test	uart_alert_test	1.380s	22.757us	1	1	100.00
V2	intr_test	uart_intr_test	1.530s	32.427us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.540s	174.017us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.540s	174.017us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.520s	46.815us	1	1	100.00
		uart_csr_rw	1.350s	13.056us	1	1	100.00
		uart_csr_aliasing	1.460s	14.302us	1	1	100.00
		uart_same_csr_outstanding	1.700s	263.718us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.520s	46.815us	1	1	100.00
		uart_csr_rw	1.350s	13.056us	1	1	100.00
		uart_csr_aliasing	1.460s	14.302us	1	1	100.00
		uart_same_csr_outstanding	1.700s	263.718us	1	1	100.00
V2		TOTAL			18	18	100.00
V2S	tl_intg_err	uart_sec_cm	1.540s	82.373us	1	1	100.00
		uart_tl_intg_err	1.610s	269.583us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.610s	269.583us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	9.090s	12.596ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00