CHIP Simulation Results

Wednesday May 14 2025 17:10:16 UTC

GitHub Revision: `70ecaeb`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.597m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.597m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	2.238m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	2.444m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	2.318m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	6.536m	5.602ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	6.536m	5.602ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	6.536m	5.602ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	37.680s	10.220us	0	1	0.00
		chip_sw_example_manufacturer	2.479m		0	1	0.00
		chip_sw_example_concurrency	4.333m	4.790ms	1	1	100.00
		chip_sw_uart_smoketest_signed	10.753s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.960s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.770s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.770s		0	1	0.00
V1	xbar_smoke	xbar_smoke	17.990s	57.760us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.509m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.344m	8.387ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	5.639m	5.813ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.301m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	1.712m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.723m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.671m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.370s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.370s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.774m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.600m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.681m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.681m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.832m	4.622ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.844m	3.155ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.844m	14.658ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.462s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.314s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.854m	14.318ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.140m	6.298ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	22.220m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	22.220m	18.016ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	30.103s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.208m	4.018ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.208m	4.018ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.343m	18.015ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.729m	5.167ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.653m	5.381ms	1	1	100.00
		chip_sw_aes_idle	3.736m	4.379ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.651m	4.221ms	1	1	100.00
		chip_sw_kmac_idle	3.919m	4.447ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.514m	12.022ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.833m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.584m	12.015ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	10.894m	12.026ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	17.150s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	19.668s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	16.200s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.019s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.903s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.446s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.361s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	17.150s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	19.668s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	16.200s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.019s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.903s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.446s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.361s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	20.319s		0	1	0.00
		chip_sw_aes_enc_jitter_en	46.130s	10.240us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	50.570s	10.300us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	53.280s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.820s	10.180us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.873s		0	1	0.00
		chip_sw_clkmgr_jitter	3.615m	5.353ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.449m	3.812ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	13.004s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	48.050s	10.360us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	51.760s	10.320us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	48.080s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	49.870s	10.160us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	54.650s	10.360us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.498s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.212s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.243s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.514s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	18.228m	15.862ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.983m	12.752ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.208m	4.018ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	16.633s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.983m	12.752ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	30.645s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	14.296s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	17.109s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	13.197s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	35.769s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	18.228m	15.862ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.844m	14.658ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	19.608m	20.024ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.533m	8.900ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	10.165m	10.577ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.221m	4.245ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	18.228m	15.862ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	14.438s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	15.998s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	18.228m	15.862ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.903s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	10.165m	10.577ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	17.746s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	17.948s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	17.694s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.413s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.993s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	18.128s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	15.998s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	1.383m		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	14.653s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	1.383m		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	1.383m		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	1.383m		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	7.236m	10.031ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.920s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.611s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	11.905s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.424s		0	1	0.00
		chip_sw_lc_ctrl_transition	1.383m		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	8.218m	9.503ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.381m	14.357ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	10.738s		0	1	0.00
		chip_prim_tl_access	9.624m	13.875ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	17.150s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	19.668s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	16.200s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	13.019s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.903s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.446s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.361s		0	1	0.00
		chip_rv_dm_lc_disabled	10.854m	14.318ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.633m	4.520ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	46.130s	10.240us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.777m	4.205ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.736m	4.379ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.016m	4.474ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	50.570s	10.300us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.651m	4.221ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.359m	4.946ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.686m	5.371ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	49.820s	10.180us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	8.218m	9.503ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	1.383m		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	39.330s	10.120us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.795m	5.899ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.919m	4.447ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	11.880s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	11.880s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	14.679s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.716m	5.028ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.117s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	8.218m	9.503ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	53.280s	10.100us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	27.882s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	20.319s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.653m	5.381ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.653m	5.381ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.653m	5.381ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.808m	5.423ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.381m	14.357ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.381m	14.357ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	8.508m	6.915ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.873s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.738s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	18.228m	15.862ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.681m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	1.383m		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.808m	5.423ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.218m	9.503ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.508m	6.915ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.019m	3.703ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.808m	5.423ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	8.218m	9.503ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	8.508m	6.915ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.019m	3.703ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	1.383m		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.084s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	14.653s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	16.920s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	13.611s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	11.905s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	13.424s		0	1	0.00
		chip_sw_lc_ctrl_transition	1.383m		0	1	0.00
		chip_prim_tl_access	9.624m	13.875ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	9.624m	13.875ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	20.891s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	14.129s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.212s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	20.319s		0	1	0.00
		chip_sw_aes_enc_jitter_en	46.130s	10.240us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	50.570s	10.300us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	53.280s	10.100us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	49.820s	10.180us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.873s		0	1	0.00
		chip_sw_clkmgr_jitter	3.615m	5.353ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	8.125m	10.028ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	8.125m	10.028ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.984m	3.662ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.390m	4.740ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	5.080m	5.317ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	9.073m	5.925ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.002m	4.752ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	4.678m	4.574ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.019m	3.703ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	19.608m	20.024ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	19.608m	20.024ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.294m	3.165ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.597m	5.138ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.002m	5.352ms	1	1	100.00
		chip_sw_csrng_smoketest	3.208m	3.063ms	1	1	100.00
		chip_sw_gpio_smoketest	3.773m	3.784ms	1	1	100.00
		chip_sw_hmac_smoketest	3.833m	3.545ms	1	1	100.00
		chip_sw_kmac_smoketest	4.281m	4.229ms	1	1	100.00
		chip_sw_otbn_smoketest	4.409m	4.294ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.051m	3.712ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.079m	5.328ms	1	1	100.00
		chip_sw_rv_timer_smoketest	3.903m	4.848ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.368m	5.149ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.235m	3.374ms	1	1	100.00
		chip_sw_uart_smoketest	2.824m	3.354ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	28.819s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	10.753s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.509m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.527s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.154m	4.749ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.957m	4.607ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.531m	4.257ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.572m	6.702ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	21.387s		0	1	0.00
		chip_rv_dm_lc_disabled	10.854m	14.318ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	19.523s		0	1	0.00
		chip_sw_lc_walkthrough_prod	28.475s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	1.225m		0	1	0.00
		chip_sw_lc_walkthrough_rma	23.904s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	21.387s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	35.885s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	26.768s		0	1	0.00
		rom_volatile_raw_unlock	10.936s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.711s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.294m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.182m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.343m	4.131ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.343m	4.131ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.770s		0	1	0.00
		chip_same_csr_outstanding	9.740s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.770s		0	1	0.00
		chip_same_csr_outstanding	9.740s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	3.100m	547.026us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	9.080s	12.300us	1	1	100.00
		xbar_smoke_large_delays	4.716m	2.526ms	1	1	100.00
		xbar_smoke_slow_rsp	4.483m	1.739ms	1	1	100.00
		xbar_random_zero_delays	1.400m	83.879us	1	1	100.00
		xbar_random_large_delays	16.021m	8.220ms	1	1	100.00
		xbar_random_slow_rsp	19.291m	7.099ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	47.200s	97.102us	1	1	100.00
		xbar_error_and_unmapped_addr	53.230s	125.064us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	52.260s	57.830us	1	1	100.00
		xbar_error_and_unmapped_addr	53.230s	125.064us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	49.170s	55.415us	1	1	100.00
		xbar_access_same_device_slow_rsp	23.149m	8.571ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	26.820s	79.498us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	1.332m	80.314us	1	1	100.00
		xbar_stress_all_with_error	2.747m	206.837us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	27.525m	1.018ms	1	1	100.00
		xbar_stress_all_with_reset_error	2.888m	210.137us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	11.795s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.160s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.022s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.696s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.814s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	11.284s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.545s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.776s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.925s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.157s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.351s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.347s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.455s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.812s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.302s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.102s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.030s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.874s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.592s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.752s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.931s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	13.872s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	13.719s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.835s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.546s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.825s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.950s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	13.077s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	13.158s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	11.865s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.618s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.094s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.235s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.311s		0	1	0.00
		rom_e2e_asm_init_dev	12.290s		0	1	0.00
		rom_e2e_asm_init_prod	11.512s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.941s		0	1	0.00
		rom_e2e_asm_init_rma	11.787s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.550s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.913s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.366s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.816s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.023m	5.486ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.843m	5.698ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	12.093s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.528s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.548s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	14.539s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	18.228m	15.862ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	12.490s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.609m	14.084ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	10.624s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.931s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	12.093s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.528s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.548s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.776s		0	1	0.00
		rom_e2e_jtag_inject_dev	11.739s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.709s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.440m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.780m	14.537ms	1	1	100.00
		chip_plic_all_irqs_0	8.994m	5.263ms	1	1	100.00
		chip_plic_all_irqs_10	9.642m	8.182ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.838m	5.708ms	1	1	100.00
		chip_sw_dma_abort	3.939m	3.640ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.544s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	12.254s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.974s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	11.250s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.968s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.788s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.965s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.558s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.746s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	12.044s		0	1	0.00
		chip_sw_mbx_smoketest	3.621m	5.366ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.50159731848600643379228568032268274826526562972867985860137826184943455133998
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (55f033)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 137.701s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.16395415880209894281993241142619855175455516349557174761212414256739648633997
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (2efc61)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 149.760s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.7373945495732262753169057174734967899245664212710351765236640650138703401139
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (5f8cf9)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 155.562s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.8477988981950669075973065204531854412267537360737357964700023014617754248637
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (c651b2)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 144.837s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.51099381589347427299298522901059057263388304644202851796446352792352292797094
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (263a02)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 145.707s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.80846050376657850771884109365377162822164029026432363307661263990400399629460
    Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.240001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.44491338052475234891030529552101667471567028380303164448629409485553954949815
    Line 413, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.26335810741630809046918752446186052832775328134265373836517451695819596383218
    Line 409, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.74975640024540854246644507011332395261904751668615273230351886376219763999455
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.64095647364239828441405731038659476867178155166608191395115105770486666313808
    Line 410, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.104094600821361102651481905574795744055866612796108668733515878988684767698489
Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12021.744167 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12021.744167 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.59939263990893217903537486699620596236530090447518888248364366437116906264851
Line 448, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12017.531022 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12017.531022 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.62163970633593799474162418809975145269813167155959197988032003548682075972784
Line 435, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12014.962860 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.962860 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.110092859316088228415540399133722416413534321785387823140824718388548867759445
Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12025.626241 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12025.626241 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.112135807543459653969229858438361249751909083856573965460847388915849099985693
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.82757913633307038473281330975748414384465617660357138700559011537675198783850
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.76271095378213750929007721782015483220511492527101455193768250704626252938762
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.75683530115404237742680404832529456727870705498603091056143761758446849063427
Line 517, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20024.470826 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20024.470826 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.98272377177470570258737031981470704026042147265098806492237718562933300070235
Line 457, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18015.804282 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18015.804282 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.81868130212111057373550861656527760748783607908529604167032113443133048064443
Line 476, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18014.532310 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18014.532310 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.66112192496080020260059071486595295346673349679379840012658855433575818999162
Line 468, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 9502.900864 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (27456817208366245181787755898910205453124601527535988158528559178270611519244 [0x3cb40200acfc30a46052ef5873e8d84c9a5429bda37ba63a1cb180ab42eab70c] vs 111733259522251708395354818474347724554805578790383279281843362059855481451830 [0xf706c8a6901a2b436a4813eef22ef791c0743c16d11065303d80a92dd452b536])
  UVM_INFO @ 9502.900864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.38219232434849706013576648126738102698173323595992233130738518183032705655197
Line 466, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 10031.431728 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (108116381536796991705866310935194805181409266070138220477924890012784305119837 [0xef07b411dd11da3d7131e591ac77f2637a45b18c0e688f41fbea90965720225d] vs 17215384320086932320561735204951818308387643620790828634982251258515127329425 [0x260f8fee10ad2c52fb3e1006d010f50547199d3fed876cf40c50b0a0eacce291])
  UVM_INFO @ 10031.431728 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.22281343699376415029681531595280660613853223851970196168712134035578784181661
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4622.120195 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'hb1378adb  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3b  a_opcode: 'h1  a_user: 'h248fa  d_param: 'h0  d_source: 'h3b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4622.120195 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.66364871120060040881779207212075189024309546420463633005012317095457220652018
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3154.834796 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46337) { a_addr: 'h30480000  a_data: 'h71b80bf2  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h12  a_opcode: 'h1  a_user: 'h248e2  d_param: 'h0  d_source: 'h12  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3154.834796 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.110379961803285291997859076532006225800634788854456110978470092954890778793114
    Line 608, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.57538983143630848620247525045711467036548180000046497470220584033215639022430
    Line 501, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5813.251962 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5813.251962 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.73019397395743924265254722249008248186334988486457275426447536890900038120466
    Line 678, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 10577.454180 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 10577.454180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.65414185900617536646490054505719592362501789948554841957840855321961444963256
    Line 460, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3661.777592 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3661.777592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.12255245742413257625910369579434866335708846316644241740324452012139419835754
    Line 501, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4740.011300 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4740.011300 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.14340846554825451862187575170860902668821506224009687712992153887377497562973
    Line 467, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4018.265240 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4018.265240 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.79482008415154058006188001539416142777012410093050672477015578078616442789546
    Line 455, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5925.047200 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5925.047200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.4154799877045800034929527536292015321760181739272962945355864246975994119056
    Line 427, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:545) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@36220) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.55037406425606270155159585731177358018475521409577923276415552619632327566695
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 4131.404150 us: (cip_base_scoreboard.sv:545) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_dbg_reg_block, TL item: req: (cip_tl_seq_item@36220) { a_addr: 'h2210  a_data: 'hd4f63afc  a_mask: 'h1  a_size: 'h2  a_param: 'h0  a_source: 'ha5  a_opcode: 'h4  a_user: 'h260ca  d_param: 'h0  d_source: 'ha5  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4131.404150 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.49415180663380171172234432355362383582875137107830155336046811343479568265893
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14657.844904 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14657.844904 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.4397880335666944371779405592604786710824343621954436016361120755295945773886
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  ../src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.89200763805850324705325625137345350460512094398309647363938977130504447091894
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3640.256700 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3640.256700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```