CSRNG Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	csrng_smoke	5.000s	27.243us	1	1	100.00
V1	csr_hw_reset	csrng_csr_hw_reset	4.000s	42.491us	1	1	100.00
V1	csr_rw	csrng_csr_rw	5.000s	63.616us	1	1	100.00
V1	csr_bit_bash	csrng_csr_bit_bash	12.000s	375.032us	1	1	100.00
V1	csr_aliasing	csrng_csr_aliasing	8.000s	297.889us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	csrng_csr_mem_rw_with_rand_reset	5.000s	61.372us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	csrng_csr_rw	5.000s	63.616us	1	1	100.00
		csrng_csr_aliasing	8.000s	297.889us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	interrupts	csrng_intr	7.000s	54.959us	1	1	100.00
V2	alerts	csrng_alert	12.000s	316.058us	1	1	100.00
V2	err	csrng_err	5.000s	43.190us	1	1	100.00
V2	cmds	csrng_cmds	2.650m	7.762ms	1	1	100.00
V2	life cycle	csrng_cmds	2.650m	7.762ms	1	1	100.00
V2	stress_all	csrng_stress_all	5.000s	43.600us	0	1	0.00
V2	intr_test	csrng_intr_test	4.000s	15.441us	1	1	100.00
V2	alert_test	csrng_alert_test	5.000s	38.724us	1	1	100.00
V2	tl_d_oob_addr_access	csrng_tl_errors	7.000s	42.313us	1	1	100.00
V2	tl_d_illegal_access	csrng_tl_errors	7.000s	42.313us	1	1	100.00
V2	tl_d_outstanding_access	csrng_csr_hw_reset	4.000s	42.491us	1	1	100.00
		csrng_csr_rw	5.000s	63.616us	1	1	100.00
		csrng_csr_aliasing	8.000s	297.889us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	17.962us	1	1	100.00
V2	tl_d_partial_access	csrng_csr_hw_reset	4.000s	42.491us	1	1	100.00
		csrng_csr_rw	5.000s	63.616us	1	1	100.00
		csrng_csr_aliasing	8.000s	297.889us	1	1	100.00
		csrng_same_csr_outstanding	5.000s	17.962us	1	1	100.00
V2		TOTAL			8	9	88.89
V2S	tl_intg_err	csrng_sec_cm	8.000s	477.757us	1	1	100.00
		csrng_tl_intg_err	16.000s	1.191ms	1	1	100.00
V2S	sec_cm_config_regwen	csrng_regwen	5.000s	14.418us	1	1	100.00
		csrng_csr_rw	5.000s	63.616us	1	1	100.00
V2S	sec_cm_config_mubi	csrng_alert	12.000s	316.058us	1	1	100.00
V2S	sec_cm_intersig_mubi	csrng_stress_all	5.000s	43.600us	0	1	0.00
V2S	sec_cm_main_sm_fsm_sparse	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
		csrng_sec_cm	8.000s	477.757us	1	1	100.00
V2S	sec_cm_update_fsm_sparse	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
		csrng_sec_cm	8.000s	477.757us	1	1	100.00
V2S	sec_cm_blk_enc_fsm_sparse	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
		csrng_sec_cm	8.000s	477.757us	1	1	100.00
V2S	sec_cm_outblk_fsm_sparse	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
		csrng_sec_cm	8.000s	477.757us	1	1	100.00
V2S	sec_cm_gen_cmd_ctr_redun	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
		csrng_sec_cm	8.000s	477.757us	1	1	100.00
V2S	sec_cm_drbg_upd_ctr_redun	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
		csrng_sec_cm	8.000s	477.757us	1	1	100.00
V2S	sec_cm_drbg_gen_ctr_redun	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
		csrng_sec_cm	8.000s	477.757us	1	1	100.00
V2S	sec_cm_ctrl_mubi	csrng_alert	12.000s	316.058us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
V2S	sec_cm_constants_lc_gated	csrng_stress_all	5.000s	43.600us	0	1	0.00
V2S	sec_cm_sw_genbits_bus_consistency	csrng_alert	12.000s	316.058us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	csrng_tl_intg_err	16.000s	1.191ms	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_sparse	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
		csrng_sec_cm	8.000s	477.757us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_redun	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
V2S	sec_cm_aes_cipher_ctrl_sparse	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
V2S	sec_cm_aes_cipher_fsm_local_esc	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
V2S	sec_cm_aes_cipher_ctr_redun	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
		csrng_sec_cm	8.000s	477.757us	1	1	100.00
V2S	sec_cm_aes_cipher_data_reg_local_esc	csrng_intr	7.000s	54.959us	1	1	100.00
		csrng_err	5.000s	43.190us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	csrng_stress_all_with_rand_reset	37.000s	1.277ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			17	19	89.47

Failure Buckets

• UVM_ERROR (csrng_scoreboard.sv:166) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq has 1 failures:

  • Test csrng_stress_all has 1 failures.

    • 0.csrng_stress_all.33787682155989964968688189464682084440060188841518607276938706008412469789671
      Line 131, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all/latest/run.log

        UVM_ERROR @  43599865 ps: (csrng_scoreboard.sv:166) [uvm_test_top.env.scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: EntropyReq
        UVM_INFO @  43599865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:929) [csrng_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test csrng_stress_all_with_rand_reset has 1 failures.

    • 0.csrng_stress_all_with_rand_reset.3093954042039640075997570194751763080682997531359854430839804219248320381909
      Line 102, in log /nightly/runs/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1277320406 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.csrng_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1277320406 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---