DMA Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	361.785us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	1.707ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	331.103us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	5.000s	34.908us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	96.614us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	11.000s	298.425us	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	4.825ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	83.643us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	96.614us	1	1	100.00
		dma_csr_aliasing	7.000s	4.825ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	24.000s	7.160ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	28.200m	176.808ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	5.917m	446.851ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	6.317m	490.245ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	28.200m	176.808ms	1	1	100.00
V2	dma_abort	dma_abort	14.000s	1.045ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	4.800m	85.954ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	152.881us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	1.596ms	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	1.596ms	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	5.000s	34.908us	1	1	100.00
		dma_csr_rw	4.000s	96.614us	1	1	100.00
		dma_csr_aliasing	7.000s	4.825ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	425.031us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	5.000s	34.908us	1	1	100.00
		dma_csr_rw	4.000s	96.614us	1	1	100.00
		dma_csr_aliasing	7.000s	4.825ms	1	1	100.00
		dma_same_csr_outstanding	5.000s	425.031us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	23.000s	71.475us	1	1	100.00
		dma_generic_stress	6.317m	490.245ms	1	1	100.00
		dma_handshake_stress	28.200m	176.808ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	172.393us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.500m	11.173ms	1	1	100.00
		dma_longer_transfer	10.000s	909.563us	1	1	100.00
		TOTAL			21	21	100.00