EDN Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.920s 29.942us 1 1 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.730s 19.008us 1 1 100.00
V1 csr_rw edn_csr_rw 1.670s 12.312us 1 1 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.370s 75.806us 1 1 100.00
V1 csr_aliasing edn_csr_aliasing 2.170s 73.220us 1 1 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.310s 28.161us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.670s 12.312us 1 1 100.00
edn_csr_aliasing 2.170s 73.220us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 firmware edn_genbits 1.880s 82.090us 1 1 100.00
V2 csrng_commands edn_genbits 1.880s 82.090us 1 1 100.00
V2 genbits edn_genbits 1.880s 82.090us 1 1 100.00
V2 interrupts edn_intr 2.270s 20.564us 1 1 100.00
V2 alerts edn_alert 1.990s 26.768us 1 1 100.00
V2 errs edn_err 1.920s 72.701us 1 1 100.00
V2 disable edn_disable 1.680s 26.025us 1 1 100.00
edn_disable_auto_req_mode 2.020s 40.355us 1 1 100.00
V2 stress_all edn_stress_all 2.880s 106.374us 1 1 100.00
V2 intr_test edn_intr_test 1.710s 38.463us 1 1 100.00
V2 alert_test edn_alert_test 1.690s 54.001us 1 1 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.210s 41.027us 1 1 100.00
V2 tl_d_illegal_access edn_tl_errors 3.210s 41.027us 1 1 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.730s 19.008us 1 1 100.00
edn_csr_rw 1.670s 12.312us 1 1 100.00
edn_csr_aliasing 2.170s 73.220us 1 1 100.00
edn_same_csr_outstanding 2.060s 60.154us 1 1 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.730s 19.008us 1 1 100.00
edn_csr_rw 1.670s 12.312us 1 1 100.00
edn_csr_aliasing 2.170s 73.220us 1 1 100.00
edn_same_csr_outstanding 2.060s 60.154us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S tl_intg_err edn_sec_cm 7.450s 1.916ms 1 1 100.00
edn_tl_intg_err 2.410s 89.401us 1 1 100.00
V2S sec_cm_config_regwen edn_regwen 1.810s 26.594us 1 1 100.00
V2S sec_cm_config_mubi edn_alert 1.990s 26.768us 1 1 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.450s 1.916ms 1 1 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.450s 1.916ms 1 1 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.450s 1.916ms 1 1 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.450s 1.916ms 1 1 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.990s 26.768us 1 1 100.00
edn_sec_cm 7.450s 1.916ms 1 1 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.990s 26.768us 1 1 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.410s 89.401us 1 1 100.00
V2S TOTAL 3 3 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 0 1 0.00
V3 TOTAL 0 1 0.00
TOTAL 20 21 95.24

Failure Buckets