HMAC Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 2.180s 82.948us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 2.060s 39.396us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.820s 20.209us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.650s 455.614us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 7.270s 4.151ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 3.250s 34.758us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.820s 20.209us 1 1 100.00
hmac_csr_aliasing 7.270s 4.151ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 27.000s 5.986ms 1 1 100.00
V2 back_pressure hmac_back_pressure 7.290s 172.274us 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.230s 519.022us 1 1 100.00
hmac_test_sha384_vectors 18.820s 445.584us 1 1 100.00
hmac_test_sha512_vectors 5.539m 20.535ms 1 1 100.00
hmac_test_hmac256_vectors 7.360s 1.047ms 1 1 100.00
hmac_test_hmac384_vectors 10.210s 334.440us 1 1 100.00
hmac_test_hmac512_vectors 10.510s 644.812us 1 1 100.00
V2 burst_wr hmac_burst_wr 9.420s 233.103us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.964m 2.244ms 1 1 100.00
V2 error hmac_error 3.400s 304.369us 1 1 100.00
V2 wipe_secret hmac_wipe_secret 23.280s 3.349ms 1 1 100.00
V2 save_and_restore hmac_smoke 2.180s 82.948us 1 1 100.00
hmac_long_msg 27.000s 5.986ms 1 1 100.00
hmac_back_pressure 7.290s 172.274us 1 1 100.00
hmac_datapath_stress 1.964m 2.244ms 1 1 100.00
hmac_burst_wr 9.420s 233.103us 1 1 100.00
hmac_stress_all 3.136m 20.545ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 2.180s 82.948us 1 1 100.00
hmac_long_msg 27.000s 5.986ms 1 1 100.00
hmac_back_pressure 7.290s 172.274us 1 1 100.00
hmac_datapath_stress 1.964m 2.244ms 1 1 100.00
hmac_wipe_secret 23.280s 3.349ms 1 1 100.00
hmac_test_sha256_vectors 8.230s 519.022us 1 1 100.00
hmac_test_sha384_vectors 18.820s 445.584us 1 1 100.00
hmac_test_sha512_vectors 5.539m 20.535ms 1 1 100.00
hmac_test_hmac256_vectors 7.360s 1.047ms 1 1 100.00
hmac_test_hmac384_vectors 10.210s 334.440us 1 1 100.00
hmac_test_hmac512_vectors 10.510s 644.812us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 2.180s 82.948us 1 1 100.00
hmac_long_msg 27.000s 5.986ms 1 1 100.00
hmac_back_pressure 7.290s 172.274us 1 1 100.00
hmac_datapath_stress 1.964m 2.244ms 1 1 100.00
hmac_burst_wr 9.420s 233.103us 1 1 100.00
hmac_error 3.400s 304.369us 1 1 100.00
hmac_wipe_secret 23.280s 3.349ms 1 1 100.00
hmac_test_sha256_vectors 8.230s 519.022us 1 1 100.00
hmac_test_sha384_vectors 18.820s 445.584us 1 1 100.00
hmac_test_sha512_vectors 5.539m 20.535ms 1 1 100.00
hmac_test_hmac256_vectors 7.360s 1.047ms 1 1 100.00
hmac_test_hmac384_vectors 10.210s 334.440us 1 1 100.00
hmac_test_hmac512_vectors 10.510s 644.812us 1 1 100.00
hmac_stress_all 3.136m 20.545ms 1 1 100.00
V2 stress_all hmac_stress_all 3.136m 20.545ms 1 1 100.00
V2 alert_test hmac_alert_test 1.490s 35.008us 1 1 100.00
V2 intr_test hmac_intr_test 1.670s 20.926us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.330s 563.878us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.330s 563.878us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 2.060s 39.396us 1 1 100.00
hmac_csr_rw 1.820s 20.209us 1 1 100.00
hmac_csr_aliasing 7.270s 4.151ms 1 1 100.00
hmac_same_csr_outstanding 2.640s 403.100us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 2.060s 39.396us 1 1 100.00
hmac_csr_rw 1.820s 20.209us 1 1 100.00
hmac_csr_aliasing 7.270s 4.151ms 1 1 100.00
hmac_same_csr_outstanding 2.640s 403.100us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.700s 316.583us 1 1 100.00
hmac_tl_intg_err 3.240s 3.275ms 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.240s 3.275ms 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 2.180s 82.948us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.010s 576.314us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.886m 14.534ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 2.570s 88.148us 1 1 100.00
TOTAL 28 28 100.00