I2C Simulation Results

Thursday May 15 2025 17:06:21 UTC

GitHub Revision: 38b1fbc

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	55.330s	1.827ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	25.910s	4.645ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.610s	83.919us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.550s	25.287us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.360s	368.020us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	1.800s	55.756us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.580s	25.336us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.550s	25.287us	1	1	100.00
		i2c_csr_aliasing	1.800s	55.756us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	1.940s	299.170us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	3.400m	24.935ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	2.716m	25.925ms	1	1	100.00
V2	host_override	i2c_host_override	1.610s	85.537us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	3.569m	4.973ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.685m	2.339ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.690s	142.934us	1	1	100.00
		i2c_host_fifo_fmt_empty	9.670s	479.533us	1	1	100.00
		i2c_host_fifo_reset_rx	3.630s	292.932us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	30.650s	4.039ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.760s	3.238ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.000s	73.065us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.600s	2.065ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	15.390s	8.646ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.510s	3.676ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	40.720s	1.369ms	1	1	100.00
		i2c_target_intr_smoke	5.570s	4.914ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.900s	208.994us	1	1	100.00
		i2c_target_fifo_reset_tx	2.120s	218.427us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	8.668m	50.811ms	1	1	100.00
		i2c_target_stress_rd	40.720s	1.369ms	1	1	100.00
		i2c_target_intr_stress_wr	20.940s	17.664ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	4.690s	4.655ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	5.360s	560.207us	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.230s	710.371us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	2.600s	609.344us	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.970s	1.906ms	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.750s	484.888us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	2.716m	25.925ms	1	1	100.00
		i2c_host_perf_precise	1.461m	23.812ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.760s	3.238ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	5.440s	476.003us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.880s	512.819us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.830s	2.275ms	1	1	100.00
		i2c_target_nack_txstretch	2.020s	169.698us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.230s	1.420ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.650s	476.222us	1	1	100.00
V2	alert_test	i2c_alert_test	1.600s	22.409us	1	1	100.00
V2	intr_test	i2c_intr_test	1.650s	51.970us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.750s	370.251us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.750s	370.251us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.610s	83.919us	1	1	100.00
		i2c_csr_rw	1.550s	25.287us	1	1	100.00
		i2c_csr_aliasing	1.800s	55.756us	1	1	100.00
		i2c_same_csr_outstanding	1.850s	97.996us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.610s	83.919us	1	1	100.00
		i2c_csr_rw	1.550s	25.287us	1	1	100.00
		i2c_csr_aliasing	1.800s	55.756us	1	1	100.00
		i2c_same_csr_outstanding	1.850s	97.996us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.800s	133.814us	1	1	100.00
		i2c_sec_cm	1.740s	128.736us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.800s	133.814us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	11.040s	3.349ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	1.640s	120.551us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	10.710s	805.691us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.36026191340769230781085198592644614865337549099964323876976420137597622344002
      Line 84, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3349010335 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 3349010335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.115693564101772177337161173930479612616254656555799528310856210544097088421807
      Line 83, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 805691195 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 805691195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:717) [scoreboard] controller_mode_wr_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.60943439165943419829192711263601119952329509604917171932583451783649057333358
      Line 129, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 24935248606 ps: (i2c_scoreboard.sv:717) [uvm_test_top.env.scoreboard] controller_mode_wr_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @1888272
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.75989910209458472527230235888790417630034130848379893593581811698194089895143
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 120551018 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 94 [0x5e])
        UVM_INFO @ 120551018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.32939474406721439400922275383363861509869874968335457322236401366730550614621
      Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @  73064621 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @15383
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.17111158136713055092053330777229143145654343688342379469625855358340116810689
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 169697542 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 169697542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---