| V1 |
smoke |
keymgr_dpe_smoke |
1.770m |
14.345ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.770s |
12.524us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
2.070s |
166.918us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
6.130s |
698.582us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
5.210s |
162.925us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.880s |
20.742us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
2.070s |
166.918us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.210s |
162.925us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.710s |
12.415us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.660s |
17.830us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
2.970s |
245.203us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
2.970s |
245.203us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.770s |
12.524us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
2.070s |
166.918us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.210s |
162.925us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.350s |
30.072us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.770s |
12.524us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
2.070s |
166.918us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
5.210s |
162.925us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.350s |
30.072us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
5.690s |
1.304ms |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
6.250s |
214.700us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
2.210s |
210.467us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
2.210s |
210.467us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
2.210s |
210.467us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
2.210s |
210.467us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
4.110s |
281.990us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
5.690s |
1.304ms |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
5.690s |
1.304ms |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |